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i965: Remove the brw_context from the visitors

Browse source 
As of this commit, nothing actually needs the brw_context.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
This commit is contained in:
Jason Ekstrand 2015-06-22 17:17:56 -07:00
parent bcaf4a3f07
commit 40801295d5
20 changed files with 86 additions and 79 deletions
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6
src/mesa/drivers/dri/i965/brw_cs.cpp
View file

@ -94,7 +94,8 @@ brw_cs_emit(struct brw_context *brw,
/* Now the main event: Visit the shader IR and generate our CS IR for it.
*/
fs_visitor v8(brw, mem_ctx, MESA_SHADER_COMPUTE, key, &prog_data->base, prog,
fs_visitor v8(brw->intelScreen->compiler, brw,
mem_ctx, MESA_SHADER_COMPUTE, key, &prog_data->base, prog,
&cp->Base, 8, st_index);
if (!v8.run_cs()) {
fail_msg = v8.fail_msg;
@ -103,7 +104,8 @@ brw_cs_emit(struct brw_context *brw,
prog_data->simd_size = 8;
}
fs_visitor v16(brw, mem_ctx, MESA_SHADER_COMPUTE, key, &prog_data->base, prog,
fs_visitor v16(brw->intelScreen->compiler, brw,
mem_ctx, MESA_SHADER_COMPUTE, key, &prog_data->base, prog,
&cp->Base, 16, st_index);
if (likely(!(INTEL_DEBUG & DEBUG_NO16)) &&
!fail_msg && !v8.simd16_unsupported &&

12
src/mesa/drivers/dri/i965/brw_fs.cpp
View file

@ -677,8 +677,7 @@ fs_visitor::no16(const char *msg)
} else {
simd16_unsupported = true;
struct brw_compiler *compiler = brw->intelScreen->compiler;
compiler->shader_perf_log(brw,
compiler->shader_perf_log(log_data,
"SIMD16 shader failed to compile: %s", msg);
}
}
@ -3769,8 +3768,7 @@ fs_visitor::allocate_registers()
fail("Failure to register allocate. Reduce number of "
"live scalar values to avoid this.");
} else {
struct brw_compiler *compiler = brw->intelScreen->compiler;
compiler->shader_perf_log(brw,
compiler->shader_perf_log(log_data,
"%s shader triggered register spilling. "
"Try reducing the number of live scalar "
"values to improve performance.\n",
@ -4006,7 +4004,8 @@ brw_wm_fs_emit(struct brw_context *brw,
/* Now the main event: Visit the shader IR and generate our FS IR for it.
*/
fs_visitor v(brw, mem_ctx, MESA_SHADER_FRAGMENT, key, &prog_data->base,
fs_visitor v(brw->intelScreen->compiler, brw,
mem_ctx, MESA_SHADER_FRAGMENT, key, &prog_data->base,
prog, &fp->Base, 8, st_index8);
if (!v.run_fs(false /* do_rep_send */)) {
if (prog) {
@ -4021,7 +4020,8 @@ brw_wm_fs_emit(struct brw_context *brw,
}
cfg_t *simd16_cfg = NULL;
fs_visitor v2(brw, mem_ctx, MESA_SHADER_FRAGMENT, key, &prog_data->base,
fs_visitor v2(brw->intelScreen->compiler, brw,
mem_ctx, MESA_SHADER_FRAGMENT, key, &prog_data->base,
prog, &fp->Base, 16, st_index16);
if (likely(!(INTEL_DEBUG & DEBUG_NO16) || brw->use_rep_send)) {
if (!v.simd16_unsupported) {

2
src/mesa/drivers/dri/i965/brw_fs.h
View file

@ -70,7 +70,7 @@ namespace brw {
class fs_visitor : public backend_shader
{
public:
fs_visitor(struct brw_context *brw,
fs_visitor(const struct brw_compiler *compiler, void *log_data,
void *mem_ctx,
gl_shader_stage stage,
const void *key,

1
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
View file

@ -535,7 +535,6 @@ setup_mrf_hack_interference(fs_visitor *v, struct ra_graph *g,
bool
fs_visitor::assign_regs(bool allow_spilling)
{
struct brw_compiler *compiler = brw->intelScreen->compiler;
/* Most of this allocation was written for a reg_width of 1
* (dispatch_width == 8). In extending to SIMD16, the code was
* left in place and it was converted to have the hardware

5
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
View file

@ -1975,7 +1975,7 @@ fs_visitor::emit_barrier()
bld.exec_all().emit(SHADER_OPCODE_BARRIER, reg_undef, payload);
}
fs_visitor::fs_visitor(struct brw_context *brw,
fs_visitor::fs_visitor(const struct brw_compiler *compiler, void *log_data,
void *mem_ctx,
gl_shader_stage stage,
const void *key,
@ -1984,7 +1984,8 @@ fs_visitor::fs_visitor(struct brw_context *brw,
struct gl_program *prog,
unsigned dispatch_width,
int shader_time_index)
: backend_shader(brw, mem_ctx, shader_prog, prog, prog_data, stage),
: backend_shader(compiler, log_data, mem_ctx,
shader_prog, prog, prog_data, stage),
key(key), prog_data(prog_data),
dispatch_width(dispatch_width),
shader_time_index(shader_time_index),

9
src/mesa/drivers/dri/i965/brw_shader.cpp
View file

@ -846,15 +846,16 @@ brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
return false;
}
backend_shader::backend_shader(struct brw_context *brw,
backend_shader::backend_shader(const struct brw_compiler *compiler,
void *log_data,
void *mem_ctx,
struct gl_shader_program *shader_prog,
struct gl_program *prog,
struct brw_stage_prog_data *stage_prog_data,
gl_shader_stage stage)
: brw(brw),
devinfo(brw->intelScreen->devinfo),
ctx(&brw->ctx),
: compiler(compiler),
log_data(log_data),
devinfo(compiler->devinfo),
shader(shader_prog ?
(struct brw_shader *)shader_prog->_LinkedShaders[stage] : NULL),
shader_prog(shader_prog),

8
src/mesa/drivers/dri/i965/brw_shader.h
View file

@ -220,7 +220,8 @@ enum instruction_scheduler_mode {
class backend_shader {
protected:
backend_shader(struct brw_context *brw,
backend_shader(const struct brw_compiler *compiler,
void *log_data,
void *mem_ctx,
struct gl_shader_program *shader_prog,
struct gl_program *prog,
@ -229,9 +230,10 @@ protected:
public:
struct brw_context * const brw;
const struct brw_compiler *compiler;
void *log_data; /* Passed to compiler->*_log functions */
const struct brw_device_info * const devinfo;
struct gl_context * const ctx;
struct brw_shader * const shader;
struct gl_shader_program * const shader_prog;
struct gl_program * const prog;

6
src/mesa/drivers/dri/i965/brw_vec4.cpp
View file

@ -1899,7 +1899,8 @@ brw_vs_emit(struct brw_context *brw,
prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
fs_visitor v(brw, mem_ctx, MESA_SHADER_VERTEX, &c->key,
fs_visitor v(brw->intelScreen->compiler, brw,
mem_ctx, MESA_SHADER_VERTEX, &c->key,
&prog_data->base.base, prog, &c->vp->program.Base,
8, st_index);
if (!v.run_vs(brw_select_clip_planes(&brw->ctx))) {
@ -1939,7 +1940,8 @@ brw_vs_emit(struct brw_context *brw,
if (!assembly) {
prog_data->base.dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT;
vec4_vs_visitor v(brw, c, prog_data, prog, mem_ctx, st_index,
vec4_vs_visitor v(brw->intelScreen->compiler,
c, prog_data, prog, mem_ctx, st_index,
!_mesa_is_gles3(&brw->ctx));
if (!v.run(brw_select_clip_planes(&brw->ctx))) {
if (prog) {

2
src/mesa/drivers/dri/i965/brw_vec4.h
View file

@ -76,7 +76,7 @@ class vec4_live_variables;
class vec4_visitor : public backend_shader, public ir_visitor
{
public:
vec4_visitor(struct brw_context *brw,
vec4_visitor(const struct brw_compiler *compiler,
struct brw_vec4_compile *c,
struct gl_program *prog,
const struct brw_vue_prog_key *key,

14
src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
View file

@ -34,13 +34,13 @@ const unsigned MAX_GS_INPUT_VERTICES = 6;
namespace brw {
vec4_gs_visitor::vec4_gs_visitor(struct brw_context *brw,
vec4_gs_visitor::vec4_gs_visitor(const struct brw_compiler *compiler,
struct brw_gs_compile *c,
struct gl_shader_program *prog,
void *mem_ctx,
bool no_spills,
int shader_time_index)
: vec4_visitor(brw, &c->base, &c->gp->program.Base, &c->key.base,
: vec4_visitor(compiler, &c->base, &c->gp->program.Base, &c->key.base,
&c->prog_data.base, prog, MESA_SHADER_GEOMETRY, mem_ctx,
no_spills, shader_time_index),
c(c)
@ -662,8 +662,8 @@ brw_gs_emit(struct brw_context *brw,
likely(!(INTEL_DEBUG & DEBUG_NO_DUAL_OBJECT_GS))) {
c->prog_data.base.dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT;
vec4_gs_visitor v(brw, c, prog, mem_ctx, true /* no_spills */,
st_index);
vec4_gs_visitor v(brw->intelScreen->compiler,
c, prog, mem_ctx, true /* no_spills */, st_index);
if (v.run(NULL /* clip planes */)) {
return generate_assembly(brw, prog, &c->gp->program.Base,
&c->prog_data.base, mem_ctx, v.cfg,
@ -704,10 +704,12 @@ brw_gs_emit(struct brw_context *brw,
const unsigned *ret = NULL;
if (brw->gen >= 7)
gs = new vec4_gs_visitor(brw, c, prog, mem_ctx, false /* no_spills */,
gs = new vec4_gs_visitor(brw->intelScreen->compiler,
c, prog, mem_ctx, false /* no_spills */,
st_index);
else
gs = new gen6_gs_visitor(brw, c, prog, mem_ctx, false /* no_spills */,
gs = new gen6_gs_visitor(brw->intelScreen->compiler,
c, prog, mem_ctx, false /* no_spills */,
st_index);
if (!gs->run(NULL /* clip planes */)) {

2
src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.h
View file

@ -68,7 +68,7 @@ namespace brw {
class vec4_gs_visitor : public vec4_visitor
{
public:
vec4_gs_visitor(struct brw_context *brw,
vec4_gs_visitor(const struct brw_compiler *compiler,
struct brw_gs_compile *c,
struct gl_shader_program *prog,
void *mem_ctx,

1
src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
View file

@ -191,7 +191,6 @@ vec4_visitor::setup_payload_interference(struct ra_graph *g,
bool
vec4_visitor::reg_allocate()
{
struct brw_compiler *compiler = brw->intelScreen->compiler;
unsigned int hw_reg_mapping[alloc.count];
int payload_reg_count = this->first_non_payload_grf;

5
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
View file

@ -3677,7 +3677,7 @@ vec4_visitor::resolve_bool_comparison(ir_rvalue *rvalue, src_reg *reg)
*reg = neg_result;
}
vec4_visitor::vec4_visitor(struct brw_context *brw,
vec4_visitor::vec4_visitor(const struct brw_compiler *compiler,
struct brw_vec4_compile *c,
struct gl_program *prog,
const struct brw_vue_prog_key *key,
@ -3687,7 +3687,8 @@ vec4_visitor::vec4_visitor(struct brw_context *brw,
void *mem_ctx,
bool no_spills,
int shader_time_index)
: backend_shader(brw, mem_ctx, shader_prog, prog, &prog_data->base, stage),
: backend_shader(compiler, NULL, mem_ctx,
shader_prog, prog, &prog_data->base, stage),
c(c),
key(key),
prog_data(prog_data),

4
src/mesa/drivers/dri/i965/brw_vec4_vs_visitor.cpp
View file

@ -211,14 +211,14 @@ vec4_vs_visitor::emit_thread_end()
}
vec4_vs_visitor::vec4_vs_visitor(struct brw_context *brw,
vec4_vs_visitor::vec4_vs_visitor(const struct brw_compiler *compiler,
struct brw_vs_compile *vs_compile,
struct brw_vs_prog_data *vs_prog_data,
struct gl_shader_program *prog,
void *mem_ctx,
int shader_time_index,
bool use_legacy_snorm_formula)
: vec4_visitor(brw, &vs_compile->base, &vs_compile->vp->program.Base,
: vec4_visitor(compiler, &vs_compile->base, &vs_compile->vp->program.Base,
&vs_compile->key.base, &vs_prog_data->base, prog,
MESA_SHADER_VERTEX,
mem_ctx, false /* no_spills */,

2
src/mesa/drivers/dri/i965/brw_vs.h
View file

@ -90,7 +90,7 @@ namespace brw {
class vec4_vs_visitor : public vec4_visitor
{
public:
vec4_vs_visitor(struct brw_context *brw,
vec4_vs_visitor(const struct brw_compiler *compiler,
struct brw_vs_compile *vs_compile,
struct brw_vs_prog_data *vs_prog_data,
struct gl_shader_program *prog,

4
src/mesa/drivers/dri/i965/gen6_gs_visitor.h
View file

@ -35,13 +35,13 @@ namespace brw {
class gen6_gs_visitor : public vec4_gs_visitor
{
public:
gen6_gs_visitor(struct brw_context *brw,
gen6_gs_visitor(const struct brw_compiler *comp,
struct brw_gs_compile *c,
struct gl_shader_program *prog,
void *mem_ctx,
bool no_spills,
int shader_time_index) :
vec4_gs_visitor(brw, c, prog, mem_ctx, no_spills, shader_time_index) {}
vec4_gs_visitor(comp, c, prog, mem_ctx, no_spills, shader_time_index) {}
protected:
virtual void assign_binding_table_offsets();

22
src/mesa/drivers/dri/i965/test_fs_cmod_propagation.cpp
View file

@ -32,7 +32,7 @@ class cmod_propagation_test : public ::testing::Test {
virtual void SetUp();
public:
struct brw_context *brw;
struct brw_compiler *compiler;
struct brw_device_info *devinfo;
struct gl_context *ctx;
struct brw_wm_prog_data *prog_data;
@ -44,31 +44,31 @@ public:
class cmod_propagation_fs_visitor : public fs_visitor
{
public:
cmod_propagation_fs_visitor(struct brw_context *brw,
cmod_propagation_fs_visitor(struct brw_compiler *compiler,
struct brw_wm_prog_data *prog_data,
struct gl_shader_program *shader_prog)
: fs_visitor(brw, NULL, MESA_SHADER_FRAGMENT, NULL, &prog_data->base,
shader_prog, (struct gl_program *) NULL, 8, -1) {}
: fs_visitor(compiler, NULL, NULL, MESA_SHADER_FRAGMENT, NULL,
&prog_data->base, shader_prog,
(struct gl_program *) NULL, 8, -1) {}
};
void cmod_propagation_test::SetUp()
{
brw = (struct brw_context *)calloc(1, sizeof(*brw));
devinfo = (struct brw_device_info *)calloc(1, sizeof(*brw));
brw->intelScreen = (struct intel_screen *)calloc(1, sizeof(*brw->intelScreen));
brw->intelScreen->devinfo = devinfo;
ctx = &brw->ctx;
ctx = (struct gl_context *)calloc(1, sizeof(*ctx));
compiler = (struct brw_compiler *)calloc(1, sizeof(*compiler));
devinfo = (struct brw_device_info *)calloc(1, sizeof(*devinfo));
compiler->devinfo = devinfo;
fp = ralloc(NULL, struct brw_fragment_program);
prog_data = ralloc(NULL, struct brw_wm_prog_data);
shader_prog = ralloc(NULL, struct gl_shader_program);
v = new cmod_propagation_fs_visitor(brw, prog_data, shader_prog);
v = new cmod_propagation_fs_visitor(compiler, prog_data, shader_prog);
_mesa_init_fragment_program(ctx, &fp->program, GL_FRAGMENT_SHADER, 0);
brw->gen = devinfo->gen = 4;
devinfo->gen = 4;
}
static fs_inst *

22
src/mesa/drivers/dri/i965/test_fs_saturate_propagation.cpp
View file

@ -32,7 +32,7 @@ class saturate_propagation_test : public ::testing::Test {
virtual void SetUp();
public:
struct brw_context *brw;
struct brw_compiler *compiler;
struct brw_device_info *devinfo;
struct gl_context *ctx;
struct brw_wm_prog_data *prog_data;
@ -44,31 +44,31 @@ public:
class saturate_propagation_fs_visitor : public fs_visitor
{
public:
saturate_propagation_fs_visitor(struct brw_context *brw,
saturate_propagation_fs_visitor(struct brw_compiler *compiler,
struct brw_wm_prog_data *prog_data,
struct gl_shader_program *shader_prog)
: fs_visitor(brw, NULL, MESA_SHADER_FRAGMENT, NULL, &prog_data->base,
shader_prog, (struct gl_program *) NULL, 8, -1) {}
: fs_visitor(compiler, NULL, NULL, MESA_SHADER_FRAGMENT, NULL,
&prog_data->base, shader_prog,
(struct gl_program *) NULL, 8, -1) {}
};
void saturate_propagation_test::SetUp()
{
brw = (struct brw_context *)calloc(1, sizeof(*brw));
devinfo = (struct brw_device_info *)calloc(1, sizeof(*brw));
brw->intelScreen = (struct intel_screen *)calloc(1, sizeof(*brw->intelScreen));
brw->intelScreen->devinfo = devinfo;
ctx = &brw->ctx;
ctx = (struct gl_context *)calloc(1, sizeof(*ctx));
compiler = (struct brw_compiler *)calloc(1, sizeof(*compiler));
devinfo = (struct brw_device_info *)calloc(1, sizeof(*devinfo));
compiler->devinfo = devinfo;
fp = ralloc(NULL, struct brw_fragment_program);
prog_data = ralloc(NULL, struct brw_wm_prog_data);
shader_prog = ralloc(NULL, struct gl_shader_program);
v = new saturate_propagation_fs_visitor(brw, prog_data, shader_prog);
v = new saturate_propagation_fs_visitor(compiler, prog_data, shader_prog);
_mesa_init_fragment_program(ctx, &fp->program, GL_FRAGMENT_SHADER, 0);
brw->gen = devinfo->gen = 4;
devinfo->gen = 4;
}
static fs_inst *

19
src/mesa/drivers/dri/i965/test_vec4_copy_propagation.cpp
View file

@ -33,7 +33,7 @@ class copy_propagation_test : public ::testing::Test {
virtual void SetUp();
public:
struct brw_context *brw;
struct brw_compiler *compiler;
struct brw_device_info *devinfo;
struct gl_context *ctx;
struct gl_shader_program *shader_prog;
@ -44,9 +44,9 @@ public:
class copy_propagation_vec4_visitor : public vec4_visitor
{
public:
copy_propagation_vec4_visitor(struct brw_context *brw,
copy_propagation_vec4_visitor(struct brw_compiler *compiler,
struct gl_shader_program *shader_prog)
: vec4_visitor(brw, NULL, NULL, NULL, NULL, shader_prog,
: vec4_visitor(compiler, NULL, NULL, NULL, NULL, shader_prog,
MESA_SHADER_VERTEX, NULL,
false /* no_spills */, -1)
{
@ -92,21 +92,20 @@ protected:
void copy_propagation_test::SetUp()
{
brw = (struct brw_context *)calloc(1, sizeof(*brw));
devinfo = (struct brw_device_info *)calloc(1, sizeof(*brw));
brw->intelScreen = (struct intel_screen *)calloc(1, sizeof(*brw->intelScreen));
brw->intelScreen->devinfo = devinfo;
ctx = &brw->ctx;
ctx = (struct gl_context *)calloc(1, sizeof(*ctx));
compiler = (struct brw_compiler *)calloc(1, sizeof(*compiler));
devinfo = (struct brw_device_info *)calloc(1, sizeof(*devinfo));
compiler->devinfo = devinfo;
vp = ralloc(NULL, struct brw_vertex_program);
shader_prog = ralloc(NULL, struct gl_shader_program);
v = new copy_propagation_vec4_visitor(brw, shader_prog);
v = new copy_propagation_vec4_visitor(compiler, shader_prog);
_mesa_init_vertex_program(ctx, &vp->program, GL_VERTEX_SHADER, 0);
brw->gen = devinfo->gen = 4;
devinfo->gen = 4;
}
static void

19
src/mesa/drivers/dri/i965/test_vec4_register_coalesce.cpp
View file

@ -35,7 +35,7 @@ class register_coalesce_test : public ::testing::Test {
virtual void SetUp();
public:
struct brw_context *brw;
struct brw_compiler *compiler;
struct brw_device_info *devinfo;
struct gl_context *ctx;
struct gl_shader_program *shader_prog;
@ -47,9 +47,9 @@ public:
class register_coalesce_vec4_visitor : public vec4_visitor
{
public:
register_coalesce_vec4_visitor(struct brw_context *brw,
register_coalesce_vec4_visitor(struct brw_compiler *compiler,
struct gl_shader_program *shader_prog)
: vec4_visitor(brw, NULL, NULL, NULL, NULL, shader_prog,
: vec4_visitor(compiler, NULL, NULL, NULL, NULL, shader_prog,
MESA_SHADER_VERTEX, NULL,
false /* no_spills */, -1)
{
@ -95,21 +95,20 @@ protected:
void register_coalesce_test::SetUp()
{
brw = (struct brw_context *)calloc(1, sizeof(*brw));
devinfo = (struct brw_device_info *)calloc(1, sizeof(*brw));
brw->intelScreen = (struct intel_screen *)calloc(1, sizeof(*brw->intelScreen));
brw->intelScreen->devinfo = devinfo;
ctx = &brw->ctx;
ctx = (struct gl_context *)calloc(1, sizeof(*ctx));
compiler = (struct brw_compiler *)calloc(1, sizeof(*compiler));
devinfo = (struct brw_device_info *)calloc(1, sizeof(*devinfo));
compiler->devinfo = devinfo;
vp = ralloc(NULL, struct brw_vertex_program);
shader_prog = ralloc(NULL, struct gl_shader_program);
v = new register_coalesce_vec4_visitor(brw, shader_prog);
v = new register_coalesce_vec4_visitor(compiler, shader_prog);
_mesa_init_vertex_program(ctx, &vp->program, GL_VERTEX_SHADER, 0);
brw->gen = devinfo->gen = 4;
devinfo->gen = 4;
}
static void