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i965: Enable the PIPE_CONTROL workaround workaround out of paranoia.

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There's scary stuff going on in PIPE_CONTROL internals, and if the
BSpec says to do this to make PIPE_CONTROL work, I'll go ahead and do
it because we'll probably never be able to debug it after the fact.

v2: Use stall at scoreboard instead of depth stall, as noted by Ken.
This commit is contained in:
Eric Anholt 2011-07-18 17:17:03 -07:00
parent dc7422405f
commit 407785d0e9
2 changed files with 29 additions and 3 deletions
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31
src/mesa/drivers/dri/intel/intel_batchbuffer.c
View file

@ -308,12 +308,29 @@ emit:
* [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
* =1, a PIPE_CONTROL with any non-zero post-sync-op is required. * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
* *
* XXX: There is also a workaround that would appear to apply to this * And the workaround for these two requires this workaround first:
* workaround, but it doesn't appear to be necessary so far:
* *
* Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
* BEFORE the pipe-control with a post-sync op and no write-cache * BEFORE the pipe-control with a post-sync op and no write-cache
* flushes. * flushes.
*
* And this last workaround is tricky because of the requirements on
* that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
* volume 2 part 1:
*
* "1 of the following must also be set:
* - Render Target Cache Flush Enable ([12] of DW1)
* - Depth Cache Flush Enable ([0] of DW1)
* - Stall at Pixel Scoreboard ([1] of DW1)
* - Depth Stall ([13] of DW1)
* - Post-Sync Operation ([13] of DW1)
* - Notify Enable ([8] of DW1)"
*
* The cache flushes require the workaround flush that triggered this
* one, so we can't use it. Depth stall would trigger the same.
* Post-sync nonzero is what triggered this second workaround, so we
* can't use that one either. Notify enable is IRQs, which aren't
* really our business. That leaves only stall at scoreboard.
*/ */
void void
intel_emit_post_sync_nonzero_flush(struct intel_context *intel) intel_emit_post_sync_nonzero_flush(struct intel_context *intel)
@ -321,6 +338,14 @@ intel_emit_post_sync_nonzero_flush(struct intel_context *intel)
if (!intel->batch.need_workaround_flush) if (!intel->batch.need_workaround_flush)
return; return;
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_PIPE_CONTROL);
OUT_BATCH(PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_STALL_AT_SCOREBOARD);
OUT_BATCH(0); /* address */
OUT_BATCH(0); /* write data */
ADVANCE_BATCH();
BEGIN_BATCH(4); BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_PIPE_CONTROL); OUT_BATCH(_3DSTATE_PIPE_CONTROL);
OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE); OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);

1
src/mesa/drivers/dri/intel/intel_reg.h
View file

@ -75,6 +75,7 @@
#define PIPE_CONTROL_VF_CACHE_INVALIDATE (1 << 4) #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1 << 4)
#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1 << 3) #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1 << 3)
#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1 << 2) #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1 << 2)
#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1 << 1)
#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1 << 0) #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1 << 0)
#define PIPE_CONTROL_PPGTT_WRITE (0 << 2) #define PIPE_CONTROL_PPGTT_WRITE (0 << 2)
#define PIPE_CONTROL_GLOBAL_GTT_WRITE (1 << 2) #define PIPE_CONTROL_GLOBAL_GTT_WRITE (1 << 2)