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radv: implement VK_AMD_shader_explicit_vertex_parameter

Browse source 
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2402
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>
This commit is contained in:
Samuel Pitoiset 2020-01-27 11:08:26 +01:00 • committed by Marge Bot
parent 663d5c1399
commit 401bfe0283
4 changed files with 20 additions and 8 deletions
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1
docs/relnotes/new_features.txt
View file

@ -4,6 +4,7 @@ GL_ARB_spirv_extensions on radeonsi.
GL_EXT_direct_state_access for compatibility profile.
VK_AMD_device_coherent_memory on RADV.
VK_AMD_mixed_attachment_samples on RADV.
VK_AMD_shader_explicit_vertex_parameter on RADV.
VK_AMD_shader_image_load_store_lod on RADV.
VK_AMD_shader_fragment_mask on RADV.
VK_EXT_subgroup_size_control on RADV.

1
src/amd/vulkan/radv_extensions.py
View file

@ -159,6 +159,7 @@ EXTENSIONS = [
Extension('VK_AMD_shader_ballot', 1, 'device->use_shader_ballot'),
Extension('VK_AMD_shader_core_properties', 1, True),
Extension('VK_AMD_shader_core_properties2', 1, True),
Extension('VK_AMD_shader_explicit_vertex_parameter', 1, True),
Extension('VK_AMD_shader_image_load_store_lod', 1, True),
Extension('VK_AMD_shader_fragment_mask', 1, True),
Extension('VK_AMD_shader_info', 1, True),

25
src/amd/vulkan/radv_pipeline.c
View file

@ -4255,13 +4255,20 @@ radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs,
gs->info.gs.vertices_out);
}
static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade, bool float16)
static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade,
bool explicit, bool float16)
{
uint32_t ps_input_cntl;
if (offset <= AC_EXP_PARAM_OFFSET_31) {
ps_input_cntl = S_028644_OFFSET(offset);
if (flat_shade)
if (flat_shade || explicit)
ps_input_cntl |= S_028644_FLAT_SHADE(1);
if (explicit) {
/* Force parameter cache to be read in passthrough
* mode.
*/
ps_input_cntl |= S_028644_OFFSET(1 << 5);
}
if (float16) {
ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) |
S_028644_ATTR0_VALID(1);
@ -4290,7 +4297,7 @@ radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
if (ps->info.ps.prim_id_input) {
unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false);
ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
++ps_offset;
}
}
@ -4299,9 +4306,9 @@ radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
ps->info.needs_multiview_view_index) {
unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
if (vs_offset != AC_EXP_PARAM_UNDEFINED)
ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false);
ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
else
ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false);
ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false, false);
++ps_offset;
}
@ -4317,14 +4324,14 @@ radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false);
ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false, false);
++ps_offset;
}
vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
if (vs_offset != AC_EXP_PARAM_UNDEFINED &&
ps->info.ps.num_input_clips_culls > 4) {
ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false);
ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false, false);
++ps_offset;
}
}
@ -4332,6 +4339,7 @@ radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.ps.input_mask; ++i) {
unsigned vs_offset;
bool flat_shade;
bool explicit;
bool float16;
if (!(ps->info.ps.input_mask & (1u << i)))
continue;
@ -4344,9 +4352,10 @@ radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
}
flat_shade = !!(ps->info.ps.flat_shaded_mask & (1u << ps_offset));
explicit = !!(ps->info.ps.explicit_shaded_mask & (1u << ps_offset));
float16 = !!(ps->info.ps.float16_shaded_mask & (1u << ps_offset));
ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade, float16);
ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade, explicit, float16);
++ps_offset;
}

1
src/amd/vulkan/radv_shader.c
View file

@ -342,6 +342,7 @@ radv_shader_compile_to_nir(struct radv_device *device,
.amd_gcn_shader = true,
.amd_image_read_write_lod = true,
.amd_shader_ballot = device->physical_device->use_shader_ballot,
.amd_shader_explicit_vertex_parameter = true,
.amd_trinary_minmax = true,
.demote_to_helper_invocation = device->physical_device->use_aco,
.derivative_group = true,