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radv: optimize the preprocess buffer size for DGC IES compute

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Using the precomputed information.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36753>
This commit is contained in:
Samuel Pitoiset 2025-08-13 08:59:35 +02:00 • committed by Marge Bot
parent e527d2d801
commit 3fb33aada6
1 changed files with 16 additions and 29 deletions
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57
src/amd/vulkan/radv_dgc.c
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@ -171,55 +171,43 @@ radv_get_sequence_size_compute(const struct radv_indirect_command_layout *layout
uint32_t *upload_size) uint32_t *upload_size)
{ {
const struct radv_device *device = container_of(layout->vk.base.device, struct radv_device, vk); const struct radv_device *device = container_of(layout->vk.base.device, struct radv_device, vk);
const struct radv_physical_device *pdev = radv_device_physical(device);
const VkGeneratedCommandsPipelineInfoEXT *pipeline_info = const VkGeneratedCommandsPipelineInfoEXT *pipeline_info =
vk_find_struct_const(pNext, GENERATED_COMMANDS_PIPELINE_INFO_EXT); vk_find_struct_const(pNext, GENERATED_COMMANDS_PIPELINE_INFO_EXT);
const VkGeneratedCommandsShaderInfoEXT *eso_info = vk_find_struct_const(pNext, GENERATED_COMMANDS_SHADER_INFO_EXT); const VkGeneratedCommandsShaderInfoEXT *eso_info = vk_find_struct_const(pNext, GENERATED_COMMANDS_SHADER_INFO_EXT);
struct radv_shader *cs = radv_dgc_get_shader(pipeline_info, eso_info, MESA_SHADER_COMPUTE); struct radv_shader *cs = radv_dgc_get_shader(pipeline_info, eso_info, MESA_SHADER_COMPUTE);
bool uses_grid_base_sgpr;
/* dispatch */ /* dispatch */
*cmd_size += 5 * 4; *cmd_size += 5 * 4;
if (cs) { if (cs) {
const struct radv_userdata_info *loc = radv_get_user_sgpr_info(cs, AC_UD_CS_GRID_SIZE); const struct radv_userdata_info *loc = radv_get_user_sgpr_info(cs, AC_UD_CS_GRID_SIZE);
if (loc->sgpr_idx != -1) {
if (device->load_grid_size_from_user_sgpr) { uses_grid_base_sgpr = loc->sgpr_idx != -1;
/* PKT3_SET_SH_REG for immediate values */
*cmd_size += 5 * 4;
} else { } else {
/* PKT3_SET_SH_REG for pointer */ /* precomputed CS size */
*cmd_size += 4 * 4; *cmd_size += ies->cs_num_dw * 4;
}
}
} else {
/* COMPUTE_PGM_{LO,RSRC1,RSRC2} */
*cmd_size += 7 * 4;
if (pdev->info.gfx_level >= GFX10) {
/* COMPUTE_PGM_RSRC3 */
*cmd_size += 3 * 4;
}
/* COMPUTE_{RESOURCE_LIMITS,NUM_THREADS_X} */
*cmd_size += 8 * 4;
/* Assume the compute shader needs grid size because we can't know the information for
* indirect pipelines.
*/
if (device->load_grid_size_from_user_sgpr) {
/* PKT3_SET_SH_REG for immediate values */
*cmd_size += 5 * 4;
} else {
/* PKT3_SET_SH_REG for pointer */
*cmd_size += 4 * 4;
}
if (ies->uses_indirect_desc_sets_sgpr) {
/* PKT3_SET_SH_REG for indirect descriptor sets pointer */ /* PKT3_SET_SH_REG for indirect descriptor sets pointer */
*cmd_size += 3 * 4; *cmd_size += 3 * 4;
} }
uses_grid_base_sgpr = ies->uses_grid_base_sgpr;
}
if (uses_grid_base_sgpr) {
if (device->load_grid_size_from_user_sgpr) {
/* PKT3_SET_SH_REG for immediate values */
*cmd_size += 5 * 4;
} else {
/* PKT3_SET_SH_REG for pointer */
*cmd_size += 4 * 4;
}
}
if (device->sqtt.bo) { if (device->sqtt.bo) {
/* sqtt markers */ /* sqtt markers */
*cmd_size += 8 * 3 * 4; *cmd_size += 8 * 3 * 4;
@ -388,13 +376,12 @@ radv_get_sequence_size(const struct radv_indirect_command_layout *layout, const
bool need_copy = false; bool need_copy = false;
if (layout->vk.dgc_info & BITFIELD_BIT(MESA_VK_DGC_IES)) { if (layout->vk.dgc_info & BITFIELD_BIT(MESA_VK_DGC_IES)) {
/* Assume the compute shader needs both user SGPRs because we can't know the information if (ies->uses_upload_sgpr) {
* for indirect pipelines.
*/
*cmd_size += 3 * 4; *cmd_size += 3 * 4;
need_copy = true; need_copy = true;
}
*cmd_size += (3 * (pipeline_layout->push_constant_size / 4)) * 4; *cmd_size += (3 * util_bitcount64(ies->inline_push_const_mask)) * 4;
} else { } else {
struct radv_shader *shaders[MESA_VULKAN_SHADER_STAGES] = {0}; struct radv_shader *shaders[MESA_VULKAN_SHADER_STAGES] = {0};
if (pipeline_info) { if (pipeline_info) {