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radeonsi: inline gfx10_emit_streamout_begin/end
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16885>
This commit is contained in:
Marek Olšák
Marge Bot
parent
002e34d860
commit
3f900df071
1 changed files with 87 additions and 130 deletions
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@ -211,70 +211,6 @@ static void si_set_streamout_targets(struct pipe_context *ctx, unsigned num_targ
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sctx->emit_cache_flush(sctx, &sctx->gfx_cs);
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}
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static void gfx10_emit_streamout_begin(struct si_context *sctx)
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{
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struct si_streamout_target **t = sctx->streamout.targets;
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struct radeon_cmdbuf *cs = &sctx->gfx_cs;
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unsigned last_target = 0;
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for (unsigned i = 0; i < sctx->streamout.num_targets; i++) {
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if (t[i])
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last_target = i;
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}
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radeon_begin(cs);
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for (unsigned i = 0; i < sctx->streamout.num_targets; i++) {
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if (!t[i])
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continue;
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t[i]->stride_in_dw = sctx->streamout.stride_in_dw[i];
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bool append = sctx->streamout.append_bitmask & (1 << i);
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uint64_t va = 0;
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if (append) {
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radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, t[i]->buf_filled_size,
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RADEON_USAGE_READ | RADEON_PRIO_SO_FILLED_SIZE);
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va = t[i]->buf_filled_size->gpu_address + t[i]->buf_filled_size_offset;
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}
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radeon_emit(PKT3(PKT3_DMA_DATA, 5, 0));
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radeon_emit(S_411_SRC_SEL(append ? V_411_SRC_ADDR_TC_L2 : V_411_DATA) |
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S_411_DST_SEL(V_411_GDS) | S_411_CP_SYNC(i == last_target));
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radeon_emit(va);
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radeon_emit(va >> 32);
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radeon_emit(4 * i); /* destination in GDS */
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radeon_emit(0);
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radeon_emit(S_415_BYTE_COUNT_GFX9(4) | S_415_DISABLE_WR_CONFIRM_GFX9(i != last_target));
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}
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radeon_end();
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sctx->streamout.begin_emitted = true;
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}
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static void gfx10_emit_streamout_end(struct si_context *sctx)
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{
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struct si_streamout_target **t = sctx->streamout.targets;
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for (unsigned i = 0; i < sctx->streamout.num_targets; i++) {
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if (!t[i])
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continue;
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uint64_t va = t[i]->buf_filled_size->gpu_address + t[i]->buf_filled_size_offset;
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/* TODO: PS_DONE doesn't ensure completion of VS if there are no PS waves. */
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si_cp_release_mem(sctx, &sctx->gfx_cs, V_028A90_PS_DONE, 0, EOP_DST_SEL_TC_L2,
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EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM, EOP_DATA_SEL_GDS,
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t[i]->buf_filled_size, va, EOP_DATA_GDS(i, 1), 0);
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t[i]->buf_filled_size_valid = true;
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}
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sctx->streamout.begin_emitted = false;
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}
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static void si_flush_vgt_streamout(struct si_context *sctx)
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{
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struct radeon_cmdbuf *cs = &sctx->gfx_cs;
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@ -315,97 +251,121 @@ static void si_emit_streamout_begin(struct si_context *sctx)
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{
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struct radeon_cmdbuf *cs = &sctx->gfx_cs;
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struct si_streamout_target **t = sctx->streamout.targets;
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uint8_t *stride_in_dw = sctx->streamout.stride_in_dw;
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unsigned i;
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si_flush_vgt_streamout(sctx);
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if (!sctx->screen->use_ngg_streamout)
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si_flush_vgt_streamout(sctx);
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radeon_begin(cs);
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for (i = 0; i < sctx->streamout.num_targets; i++) {
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for (unsigned i = 0; i < sctx->streamout.num_targets; i++) {
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if (!t[i])
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continue;
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t[i]->stride_in_dw = stride_in_dw[i];
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t[i]->stride_in_dw = sctx->streamout.stride_in_dw[i];
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/* AMD GCN binds streamout buffers as shader resources.
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* VGT only counts primitives and tells the shader
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* through SGPRs what to do. */
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radeon_set_context_reg_seq(R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16 * i, 2);
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radeon_emit((t[i]->b.buffer_offset + t[i]->b.buffer_size) >> 2); /* BUFFER_SIZE (in DW) */
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radeon_emit(stride_in_dw[i]); /* VTX_STRIDE (in DW) */
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if (sctx->screen->use_ngg_streamout) {
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bool append = sctx->streamout.append_bitmask & (1 << i);
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uint64_t va = 0;
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if (sctx->streamout.append_bitmask & (1 << i) && t[i]->buf_filled_size_valid) {
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uint64_t va = t[i]->buf_filled_size->gpu_address + t[i]->buf_filled_size_offset;
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if (append) {
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radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, t[i]->buf_filled_size,
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RADEON_USAGE_READ | RADEON_PRIO_SO_FILLED_SIZE);
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/* Append. */
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radeon_emit(PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
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radeon_emit(STRMOUT_SELECT_BUFFER(i) |
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STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
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radeon_emit(0); /* unused */
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radeon_emit(0); /* unused */
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radeon_emit(va); /* src address lo */
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radeon_emit(va >> 32); /* src address hi */
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va = t[i]->buf_filled_size->gpu_address + t[i]->buf_filled_size_offset;
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}
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radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, t[i]->buf_filled_size,
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RADEON_USAGE_READ | RADEON_PRIO_SO_FILLED_SIZE);
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radeon_begin(cs);
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radeon_emit(PKT3(PKT3_DMA_DATA, 5, 0));
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radeon_emit(S_411_SRC_SEL(append ? V_411_SRC_ADDR_TC_L2 : V_411_DATA) |
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S_411_DST_SEL(V_411_GDS) | S_411_CP_SYNC(1));
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radeon_emit(va);
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radeon_emit(va >> 32);
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radeon_emit(4 * i); /* destination in GDS */
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radeon_emit(0);
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radeon_emit(S_415_BYTE_COUNT_GFX9(4));
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radeon_end();
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} else {
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/* Start from the beginning. */
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radeon_emit(PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
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radeon_emit(STRMOUT_SELECT_BUFFER(i) |
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STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
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radeon_emit(0); /* unused */
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radeon_emit(0); /* unused */
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radeon_emit(t[i]->b.buffer_offset >> 2); /* buffer offset in DW */
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radeon_emit(0); /* unused */
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/* Legacy streamout.
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*
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* The hw binds streamout buffers as shader resources. VGT only counts primitives
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* and tells the shader through SGPRs what to do.
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*/
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radeon_begin(cs);
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radeon_set_context_reg_seq(R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16 * i, 2);
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radeon_emit((t[i]->b.buffer_offset + t[i]->b.buffer_size) >> 2); /* BUFFER_SIZE (in DW) */
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radeon_emit(sctx->streamout.stride_in_dw[i]); /* VTX_STRIDE (in DW) */
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if (sctx->streamout.append_bitmask & (1 << i) && t[i]->buf_filled_size_valid) {
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uint64_t va = t[i]->buf_filled_size->gpu_address + t[i]->buf_filled_size_offset;
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/* Append. */
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radeon_emit(PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
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radeon_emit(STRMOUT_SELECT_BUFFER(i) |
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STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
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radeon_emit(0); /* unused */
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radeon_emit(0); /* unused */
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radeon_emit(va); /* src address lo */
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radeon_emit(va >> 32); /* src address hi */
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radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, t[i]->buf_filled_size,
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RADEON_USAGE_READ | RADEON_PRIO_SO_FILLED_SIZE);
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} else {
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/* Start from the beginning. */
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radeon_emit(PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
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radeon_emit(STRMOUT_SELECT_BUFFER(i) |
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STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
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radeon_emit(0); /* unused */
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radeon_emit(0); /* unused */
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radeon_emit(t[i]->b.buffer_offset >> 2); /* buffer offset in DW */
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radeon_emit(0); /* unused */
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}
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radeon_end_update_context_roll(sctx);
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}
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}
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radeon_end();
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sctx->streamout.begin_emitted = true;
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}
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void si_emit_streamout_end(struct si_context *sctx)
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{
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if (sctx->screen->use_ngg_streamout) {
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gfx10_emit_streamout_end(sctx);
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return;
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}
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struct radeon_cmdbuf *cs = &sctx->gfx_cs;
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struct si_streamout_target **t = sctx->streamout.targets;
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unsigned i;
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uint64_t va;
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si_flush_vgt_streamout(sctx);
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if (!sctx->screen->use_ngg_streamout)
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si_flush_vgt_streamout(sctx);
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radeon_begin(cs);
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for (i = 0; i < sctx->streamout.num_targets; i++) {
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for (unsigned i = 0; i < sctx->streamout.num_targets; i++) {
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if (!t[i])
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continue;
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va = t[i]->buf_filled_size->gpu_address + t[i]->buf_filled_size_offset;
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radeon_emit(PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
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radeon_emit(STRMOUT_SELECT_BUFFER(i) | STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
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STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
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radeon_emit(va); /* dst address lo */
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radeon_emit(va >> 32); /* dst address hi */
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radeon_emit(0); /* unused */
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radeon_emit(0); /* unused */
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uint64_t va = t[i]->buf_filled_size->gpu_address + t[i]->buf_filled_size_offset;
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radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, t[i]->buf_filled_size,
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RADEON_USAGE_WRITE | RADEON_PRIO_SO_FILLED_SIZE);
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if (sctx->screen->use_ngg_streamout) {
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/* TODO: PS_DONE doesn't ensure completion of VS if there are no PS waves. */
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si_cp_release_mem(sctx, &sctx->gfx_cs, V_028A90_PS_DONE, 0, EOP_DST_SEL_TC_L2,
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EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM, EOP_DATA_SEL_GDS,
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t[i]->buf_filled_size, va, EOP_DATA_GDS(i, 1), 0);
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} else {
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radeon_begin(cs);
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radeon_emit(PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
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radeon_emit(STRMOUT_SELECT_BUFFER(i) | STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
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STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
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radeon_emit(va); /* dst address lo */
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radeon_emit(va >> 32); /* dst address hi */
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radeon_emit(0); /* unused */
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radeon_emit(0); /* unused */
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/* Zero the buffer size. The counters (primitives generated,
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* primitives emitted) may be enabled even if there is not
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* buffer bound. This ensures that the primitives-emitted query
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* won't increment. */
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radeon_set_context_reg(R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16 * i, 0);
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/* Zero the buffer size. The counters (primitives generated,
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* primitives emitted) may be enabled even if there is not
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* buffer bound. This ensures that the primitives-emitted query
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* won't increment. */
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radeon_set_context_reg(R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16 * i, 0);
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radeon_end_update_context_roll(sctx);
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radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, t[i]->buf_filled_size,
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RADEON_USAGE_WRITE | RADEON_PRIO_SO_FILLED_SIZE);
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}
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t[i]->buf_filled_size_valid = true;
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}
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radeon_end_update_context_roll(sctx);
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sctx->streamout.begin_emitted = false;
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}
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@ -474,11 +434,8 @@ void si_init_streamout_functions(struct si_context *sctx)
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sctx->b.create_stream_output_target = si_create_so_target;
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sctx->b.stream_output_target_destroy = si_so_target_destroy;
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sctx->b.set_stream_output_targets = si_set_streamout_targets;
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sctx->atoms.s.streamout_begin.emit = si_emit_streamout_begin;
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if (sctx->screen->use_ngg_streamout) {
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sctx->atoms.s.streamout_begin.emit = gfx10_emit_streamout_begin;
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} else {
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sctx->atoms.s.streamout_begin.emit = si_emit_streamout_begin;
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if (!sctx->screen->use_ngg_streamout)
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sctx->atoms.s.streamout_enable.emit = si_emit_streamout_enable;
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}
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}
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