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i965: drop state_bo references to batch_bo

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As we use state relocations and we know that all the state belongs to
the same bo, we can drop the multiple references to the same bo.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Chris Wilson 2011-02-10 18:31:13 +00:00
parent 1be3764dbe
commit 3f55683927
9 changed files with 74 additions and 105 deletions
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6
src/mesa/drivers/dri/i965/brw_cc.c
View file

@ -35,6 +35,7 @@
#include "brw_defines.h"
#include "brw_util.h"
#include "main/macros.h"
#include "intel_batchbuffer.h"
void
brw_update_cc_vp(struct brw_context *brw)
@ -94,8 +95,7 @@ static void upload_cc_unit(struct brw_context *brw)
struct gl_context *ctx = &brw->intel.ctx;
struct brw_cc_unit_state *cc;
cc = brw_state_batch(brw, sizeof(*cc), 64,
&brw->cc.state_bo, &brw->cc.state_offset);
cc = brw_state_batch(brw, sizeof(*cc), 64, &brw->cc.state_offset);
memset(cc, 0, sizeof(*cc));
/* _NEW_STENCIL */
@ -214,7 +214,7 @@ static void upload_cc_unit(struct brw_context *brw)
brw->state.dirty.cache |= CACHE_NEW_CC_UNIT;
/* Emit CC viewport relocation */
drm_intel_bo_emit_reloc(brw->cc.state_bo,
drm_intel_bo_emit_reloc(brw->intel.batch->buf,
(brw->cc.state_offset +
offsetof(struct brw_cc_unit_state, cc4)),
brw->cc.vp_bo, 0,

5
src/mesa/drivers/dri/i965/brw_context.h
View file

@ -602,9 +602,7 @@ struct brw_context
drm_intel_bo *const_bo;
/** Binding table of pointers to surf_bo entries */
drm_intel_bo *bind_bo;
uint32_t bind_bo_offset;
drm_intel_bo *surf_bo[BRW_VS_MAX_SURF];
uint32_t surf_offset[BRW_VS_MAX_SURF];
GLuint nr_surfaces;
} vs;
@ -656,9 +654,7 @@ struct brw_context
drm_intel_bo *sampler_bo;
/** Binding table of pointers to surf_bo entries */
drm_intel_bo *bind_bo;
uint32_t bind_bo_offset;
drm_intel_bo *surf_bo[BRW_WM_MAX_SURF];
uint32_t surf_offset[BRW_WM_MAX_SURF];
drm_intel_bo *prog_bo;
@ -683,7 +679,6 @@ struct brw_context
drm_intel_bo *depth_stencil_state_bo;
drm_intel_bo *color_calc_state_bo;
drm_intel_bo *state_bo;
uint32_t state_offset;
} cc;

2
src/mesa/drivers/dri/i965/brw_misc_state.c
View file

@ -151,7 +151,7 @@ static void upload_pipelined_state_pointers(struct brw_context *brw )
OUT_RELOC(brw->clip.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
OUT_RELOC(brw->sf.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
OUT_RELOC(brw->wm.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
OUT_RELOC(brw->cc.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
OUT_RELOC(brw->intel.batch->buf, I915_GEM_DOMAIN_INSTRUCTION, 0,
brw->cc.state_offset);
ADVANCE_BATCH();

2
src/mesa/drivers/dri/i965/brw_state.h
View file

@ -176,14 +176,12 @@ void brw_clear_batch_cache( struct brw_context *brw );
void *brw_state_batch(struct brw_context *brw,
int size,
int alignment,
drm_intel_bo **out_bo,
uint32_t *out_offset);
/* brw_wm_surface_state.c */
void brw_create_constant_surface(struct brw_context *brw,
drm_intel_bo *bo,
int width,
drm_intel_bo **out_bo,
uint32_t *out_offset);
#endif

7
src/mesa/drivers/dri/i965/brw_state_batch.c
View file

@ -116,7 +116,6 @@ void *
brw_state_batch(struct brw_context *brw,
int size,
int alignment,
drm_intel_bo **out_bo,
uint32_t *out_offset)
{
struct intel_batchbuffer *batch = brw->intel.batch;
@ -137,12 +136,6 @@ brw_state_batch(struct brw_context *brw,
batch->state_batch_offset = offset;
if (*out_bo != batch->buf) {
drm_intel_bo_unreference(*out_bo);
drm_intel_bo_reference(batch->buf);
*out_bo = batch->buf;
}
*out_offset = offset;
return batch->map + offset;
}

49
src/mesa/drivers/dri/i965/brw_state_dump.c
View file

@ -26,6 +26,7 @@
*/
#include "main/mtypes.h"
#include "intel_batchbuffer.h"
#include "brw_context.h"
#include "brw_defines.h"
@ -54,7 +55,8 @@ state_out(const char *name, void *data, uint32_t hw_offset, int index,
/** Generic, undecoded state buffer debug printout */
static void
state_struct_out(const char *name, drm_intel_bo *buffer, unsigned int state_size)
state_struct_out(const char *name, drm_intel_bo *buffer,
unsigned int offset, unsigned int size)
{
int i;
@ -62,8 +64,8 @@ state_struct_out(const char *name, drm_intel_bo *buffer, unsigned int state_size
return;
drm_intel_bo_map(buffer, GL_FALSE);
for (i = 0; i < state_size / 4; i++) {
state_out(name, buffer->virtual, buffer->offset, i,
for (i = 0; i < size / 4; i++) {
state_out(name, buffer->virtual + offset, buffer->offset + offset, i,
"dword %d\n", i);
}
drm_intel_bo_unmap(buffer);
@ -98,21 +100,25 @@ get_965_surface_format(unsigned int surface_format)
static void dump_wm_surface_state(struct brw_context *brw)
{
dri_bo *bo;
GLubyte *base;
int i;
bo = brw->intel.batch->buf;
drm_intel_bo_map(bo, GL_FALSE);
base = bo->virtual;
for (i = 0; i < brw->wm.nr_surfaces; i++) {
drm_intel_bo *surf_bo = brw->wm.surf_bo[i];
unsigned int surfoff;
struct brw_surface_state *surf;
char name[20];
if (surf_bo == NULL) {
if (brw->wm.surf_offset[i] == 0) {
fprintf(stderr, "WM SURF%d: NULL\n", i);
continue;
}
drm_intel_bo_map(surf_bo, GL_FALSE);
surfoff = surf_bo->offset + brw->wm.surf_offset[i];
surf = (struct brw_surface_state *)(surf_bo->virtual + brw->wm.surf_offset[i]);
surfoff = bo->offset + brw->wm.surf_offset[i];
surf = (struct brw_surface_state *)(base + brw->wm.surf_offset[i]);
sprintf(name, "WM SURF%d", i);
state_out(name, surf, surfoff, 0, "%s %s\n",
@ -127,9 +133,8 @@ static void dump_wm_surface_state(struct brw_context *brw)
surf->ss4.min_lod);
state_out(name, surf, surfoff, 5, "x,y offset: %d,%d\n",
surf->ss5.x_offset, surf->ss5.y_offset);
drm_intel_bo_unmap(surf_bo);
}
drm_intel_bo_unmap(bo);
}
@ -280,13 +285,14 @@ static void dump_cc_state(struct brw_context *brw)
const char *name = "CC";
struct gen6_color_calc_state *cc;
uint32_t cc_off;
dri_bo *bo = brw->intel.batch->buf;
if (brw->cc.state_bo == NULL)
if (brw->cc.state_offset == 0)
return;
drm_intel_bo_map(brw->cc.state_bo, GL_FALSE);
cc = brw->cc.state_bo->virtual;
cc_off = brw->cc.state_bo->offset;
drm_intel_bo_map(bo, GL_FALSE);
cc = bo->virtual;
cc_off = bo->offset;
state_out(name, cc, cc_off, 0, "alpha test format %s, round disable %d, stencil ref %d,"
"bf stencil ref %d\n",
@ -300,7 +306,7 @@ static void dump_cc_state(struct brw_context *brw)
state_out(name, cc, cc_off, 4, "constant blue %f\n", cc->constant_b);
state_out(name, cc, cc_off, 5, "constant alpha %f\n", cc->constant_a);
drm_intel_bo_unmap(brw->cc.state_bo);
drm_intel_bo_unmap(bo);
}
@ -369,26 +375,29 @@ void brw_debug_batch(struct intel_context *intel)
{
struct brw_context *brw = brw_context(&intel->ctx);
state_struct_out("WM bind", brw->wm.bind_bo, 4 * brw->wm.nr_surfaces);
state_struct_out("WM bind",
brw->intel.batch->buf,
brw->wm.bind_bo_offset,
4 * brw->wm.nr_surfaces);
dump_wm_surface_state(brw);
dump_wm_sampler_state(brw);
if (intel->gen < 6)
state_struct_out("VS", brw->vs.state_bo, sizeof(struct brw_vs_unit_state));
state_struct_out("VS", brw->vs.state_bo, 0, sizeof(struct brw_vs_unit_state));
brw_debug_prog("VS prog", brw->vs.prog_bo);
if (intel->gen < 6)
state_struct_out("GS", brw->gs.state_bo, sizeof(struct brw_gs_unit_state));
state_struct_out("GS", brw->gs.state_bo, 0, sizeof(struct brw_gs_unit_state));
brw_debug_prog("GS prog", brw->gs.prog_bo);
if (intel->gen < 6) {
state_struct_out("SF", brw->sf.state_bo, sizeof(struct brw_sf_unit_state));
state_struct_out("SF", brw->sf.state_bo, 0, sizeof(struct brw_sf_unit_state));
brw_debug_prog("SF prog", brw->sf.prog_bo);
}
dump_sf_viewport_state(brw);
if (intel->gen < 6)
state_struct_out("WM", brw->wm.state_bo, sizeof(struct brw_wm_unit_state));
state_struct_out("WM", brw->wm.state_bo, 0, sizeof(struct brw_wm_unit_state));
brw_debug_prog("WM prog", brw->wm.prog_bo);
if (intel->gen >= 6) {

17
src/mesa/drivers/dri/i965/brw_vs_surface_state.c
View file

@ -124,13 +124,11 @@ brw_update_vs_constant_surface( struct gl_context *ctx,
* it.
*/
if (brw->vs.const_bo == NULL) {
drm_intel_bo_unreference(brw->vs.surf_bo[surf]);
brw->vs.surf_bo[surf] = NULL;
brw->vs.surf_offset[surf] = 0;
return;
}
brw_create_constant_surface(brw, brw->vs.const_bo, params->NumParameters,
&brw->vs.surf_bo[surf],
&brw->vs.surf_offset[surf]);
}
@ -166,11 +164,10 @@ static void upload_vs_surfaces(struct brw_context *brw)
/* BRW_NEW_NR_VS_SURFACES */
if (brw->vs.nr_surfaces == 0) {
if (brw->vs.bind_bo) {
drm_intel_bo_unreference(brw->vs.bind_bo);
brw->vs.bind_bo = NULL;
if (brw->vs.bind_bo_offset) {
brw->state.dirty.brw |= BRW_NEW_BINDING_TABLE;
}
brw->vs.bind_bo_offset = 0;
return;
}
@ -180,15 +177,11 @@ static void upload_vs_surfaces(struct brw_context *brw)
* space for the binding table. (once we have vs samplers)
*/
bind = brw_state_batch(brw, sizeof(uint32_t) * BRW_VS_MAX_SURF,
32, &brw->vs.bind_bo, &brw->vs.bind_bo_offset);
32, &brw->vs.bind_bo_offset);
for (i = 0; i < BRW_VS_MAX_SURF; i++) {
/* BRW_NEW_VS_CONSTBUF */
if (brw->vs.surf_bo[i]) {
bind[i] = brw->vs.surf_offset[i];
} else {
bind[i] = 0;
}
bind[i] = brw->vs.surf_offset[i];
}
brw->state.dirty.brw |= BRW_NEW_BINDING_TABLE;

5
src/mesa/drivers/dri/i965/brw_vtbl.c
View file

@ -78,7 +78,6 @@ static void brw_destroy_context( struct intel_context *intel )
dri_bo_release(&brw->curbe.curbe_bo);
dri_bo_release(&brw->vs.prog_bo);
dri_bo_release(&brw->vs.state_bo);
dri_bo_release(&brw->vs.bind_bo);
dri_bo_release(&brw->vs.const_bo);
dri_bo_release(&brw->gs.prog_bo);
dri_bo_release(&brw->gs.state_bo);
@ -90,16 +89,12 @@ static void brw_destroy_context( struct intel_context *intel )
dri_bo_release(&brw->sf.vp_bo);
for (i = 0; i < BRW_MAX_TEX_UNIT; i++)
dri_bo_release(&brw->wm.sdc_bo[i]);
dri_bo_release(&brw->wm.bind_bo);
for (i = 0; i < BRW_WM_MAX_SURF; i++)
dri_bo_release(&brw->wm.surf_bo[i]);
dri_bo_release(&brw->wm.sampler_bo);
dri_bo_release(&brw->wm.prog_bo);
dri_bo_release(&brw->wm.state_bo);
dri_bo_release(&brw->wm.const_bo);
dri_bo_release(&brw->wm.push_const_bo);
dri_bo_release(&brw->cc.prog_bo);
dri_bo_release(&brw->cc.state_bo);
dri_bo_release(&brw->cc.vp_bo);
dri_bo_release(&brw->cc.blend_state_bo);
dri_bo_release(&brw->cc.depth_stencil_state_bo);

86
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
View file

@ -191,7 +191,6 @@ brw_update_texture_surface( struct gl_context *ctx, GLuint unit )
struct brw_surface_state *surf;
surf = brw_state_batch(brw, sizeof(*surf), 32,
&brw->wm.surf_bo[surf_index],
&brw->wm.surf_offset[surf_index]);
memset(surf, 0, sizeof(*surf));
@ -225,7 +224,7 @@ brw_update_texture_surface( struct gl_context *ctx, GLuint unit )
}
/* Emit relocation to surface contents */
drm_intel_bo_emit_reloc(brw->wm.surf_bo[surf_index],
drm_intel_bo_emit_reloc(brw->intel.batch->buf,
brw->wm.surf_offset[surf_index] +
offsetof(struct brw_surface_state, ss1),
intelObj->mt->region->buffer, 0,
@ -240,14 +239,13 @@ void
brw_create_constant_surface(struct brw_context *brw,
drm_intel_bo *bo,
int width,
drm_intel_bo **out_bo,
uint32_t *out_offset)
{
struct intel_context *intel = &brw->intel;
const GLint w = width - 1;
struct brw_surface_state *surf;
surf = brw_state_batch(brw, sizeof(*surf), 32, out_bo, out_offset);
surf = brw_state_batch(brw, sizeof(*surf), 32, out_offset);
memset(surf, 0, sizeof(*surf));
surf->ss0.mipmap_layout_mode = BRW_SURFACE_MIPMAPLAYOUT_BELOW;
@ -270,8 +268,9 @@ brw_create_constant_surface(struct brw_context *brw,
* bspec ("Data Cache") says that the data cache does not exist as
* a separate cache and is just the sampler cache.
*/
drm_intel_bo_emit_reloc(*out_bo, (*out_offset +
offsetof(struct brw_surface_state, ss1)),
drm_intel_bo_emit_reloc(brw->intel.batch->buf,
(*out_offset +
offsetof(struct brw_surface_state, ss1)),
bo, 0,
I915_GEM_DOMAIN_SAMPLER, 0);
}
@ -350,16 +349,14 @@ static void upload_wm_constant_surface(struct brw_context *brw )
* it.
*/
if (brw->wm.const_bo == 0) {
if (brw->wm.surf_bo[surf] != NULL) {
drm_intel_bo_unreference(brw->wm.surf_bo[surf]);
brw->wm.surf_bo[surf] = NULL;
if (brw->wm.surf_offset[surf]) {
brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
brw->wm.surf_offset[surf] = 0;
}
return;
}
brw_create_constant_surface(brw, brw->wm.const_bo, params->NumParameters,
&brw->wm.surf_bo[surf],
&brw->wm.surf_offset[surf]);
brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
}
@ -381,7 +378,6 @@ brw_update_null_renderbuffer_surface(struct brw_context *brw, unsigned int unit)
struct brw_surface_state *surf;
surf = brw_state_batch(brw, sizeof(*surf), 32,
&brw->wm.surf_bo[unit],
&brw->wm.surf_offset[unit]);
memset(surf, 0, sizeof(*surf));
@ -412,10 +408,11 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
struct gl_context *ctx = &intel->ctx;
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
struct intel_region *region = irb->region;
struct brw_surface_state surf;
void *map;
struct brw_surface_state *surf;
memset(&surf, 0, sizeof(surf));
surf = brw_state_batch(brw, sizeof(*surf), 32,
&brw->wm.surf_offset[unit]);
memset(surf, 0, sizeof(*surf));
switch (irb->Base.Format) {
case MESA_FORMAT_XRGB8888:
@ -426,24 +423,24 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
* cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is
* used.
*/
surf.ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
surf->ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
break;
case MESA_FORMAT_SARGB8:
/* without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB
surfaces to the blend/update as sRGB */
if (ctx->Color.sRGBEnabled)
surf.ss0.surface_format = brw_format_for_mesa_format[irb->Base.Format];
surf->ss0.surface_format = brw_format_for_mesa_format[irb->Base.Format];
else
surf.ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
surf->ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
break;
default:
surf.ss0.surface_format = brw_format_for_mesa_format[irb->Base.Format];
assert(surf.ss0.surface_format != 0);
surf->ss0.surface_format = brw_format_for_mesa_format[irb->Base.Format];
assert(surf->ss0.surface_format != 0);
}
surf.ss0.surface_type = BRW_SURFACE_2D;
surf->ss0.surface_type = BRW_SURFACE_2D;
if (region->tiling == I915_TILING_NONE) {
surf.ss1.base_addr = (region->draw_x +
surf->ss1.base_addr = (region->draw_x +
region->draw_y * region->pitch) * region->cpp;
} else {
uint32_t tile_base, tile_x, tile_y;
@ -467,43 +464,38 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
/* Note that the low bits of these fields are missing, so
* there's the possibility of getting in trouble.
*/
surf.ss1.base_addr = tile_base;
surf.ss5.x_offset = tile_x / 4;
surf.ss5.y_offset = tile_y / 2;
surf->ss1.base_addr = tile_base;
surf->ss5.x_offset = tile_x / 4;
surf->ss5.y_offset = tile_y / 2;
}
surf.ss1.base_addr += region->buffer->offset; /* reloc */
surf->ss1.base_addr += region->buffer->offset; /* reloc */
surf.ss2.width = rb->Width - 1;
surf.ss2.height = rb->Height - 1;
brw_set_surface_tiling(&surf, region->tiling);
surf.ss3.pitch = (region->pitch * region->cpp) - 1;
surf->ss2.width = rb->Width - 1;
surf->ss2.height = rb->Height - 1;
brw_set_surface_tiling(surf, region->tiling);
surf->ss3.pitch = (region->pitch * region->cpp) - 1;
if (intel->gen < 6) {
/* _NEW_COLOR */
surf.ss0.color_blend = (!ctx->Color._LogicOpEnabled &&
surf->ss0.color_blend = (!ctx->Color._LogicOpEnabled &&
(ctx->Color.BlendEnabled & (1 << unit)));
surf.ss0.writedisable_red = !ctx->Color.ColorMask[unit][0];
surf.ss0.writedisable_green = !ctx->Color.ColorMask[unit][1];
surf.ss0.writedisable_blue = !ctx->Color.ColorMask[unit][2];
surf->ss0.writedisable_red = !ctx->Color.ColorMask[unit][0];
surf->ss0.writedisable_green = !ctx->Color.ColorMask[unit][1];
surf->ss0.writedisable_blue = !ctx->Color.ColorMask[unit][2];
/* As mentioned above, disable writes to the alpha component when the
* renderbuffer is XRGB.
*/
if (ctx->DrawBuffer->Visual.alphaBits == 0)
surf.ss0.writedisable_alpha = 1;
surf->ss0.writedisable_alpha = 1;
else
surf.ss0.writedisable_alpha = !ctx->Color.ColorMask[unit][3];
surf->ss0.writedisable_alpha = !ctx->Color.ColorMask[unit][3];
}
map = brw_state_batch(brw, sizeof(surf), 32,
&brw->wm.surf_bo[unit],
&brw->wm.surf_offset[unit]);
memcpy(map, &surf, sizeof(surf));
drm_intel_bo_emit_reloc(brw->wm.surf_bo[unit],
drm_intel_bo_emit_reloc(brw->intel.batch->buf,
brw->wm.surf_offset[unit] +
offsetof(struct brw_surface_state, ss1),
region->buffer,
surf.ss1.base_addr - region->buffer->offset,
surf->ss1.base_addr - region->buffer->offset,
I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER);
}
@ -591,8 +583,7 @@ upload_wm_surfaces(struct brw_context *brw)
if (texUnit->_ReallyEnabled) {
brw_update_texture_surface(ctx, i);
} else {
drm_intel_bo_unreference(brw->wm.surf_bo[surf]);
brw->wm.surf_bo[surf] = NULL;
brw->wm.surf_offset[surf] = 0;
}
}
@ -625,16 +616,11 @@ brw_wm_upload_binding_table(struct brw_context *brw)
* space for the binding table.
*/
bind = brw_state_batch(brw, sizeof(uint32_t) * BRW_WM_MAX_SURF,
32, &brw->wm.bind_bo, &brw->wm.bind_bo_offset);
32, &brw->wm.bind_bo_offset);
for (i = 0; i < BRW_WM_MAX_SURF; i++) {
/* BRW_NEW_WM_SURFACES */
bind[i] = brw->wm.surf_offset[i];
if (brw->wm.surf_bo[i]) {
bind[i] = brw->wm.surf_offset[i];
} else {
bind[i] = 0;
}
}
brw->state.dirty.brw |= BRW_NEW_BINDING_TABLE;