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radeonsi: Only enable SEs that the device reports

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Matches PAL behavior.

Cc: mesa-stable
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28196>
This commit is contained in:
Friedrich Vock 2024-03-15 03:15:10 +01:00 • committed by Marge Bot
parent bad41f4db7
commit 3f1cb470f0
1 changed files with 6 additions and 8 deletions
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14
src/gallium/drivers/radeonsi/si_state.c
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@ -6274,11 +6274,10 @@ static void gfx10_init_gfx_preamble_state(struct si_context *sctx)
/* Compute registers. */
si_pm4_set_reg(pm4, R_00B834_COMPUTE_PGM_HI, S_00B834_DATA(sscreen->info.address32_hi >> 8));
si_pm4_set_reg(pm4, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, compute_cu_en);
si_pm4_set_reg(pm4, R_00B85C_COMPUTE_STATIC_THREAD_MGMT_SE1, compute_cu_en);
si_pm4_set_reg(pm4, R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, compute_cu_en);
si_pm4_set_reg(pm4, R_00B868_COMPUTE_STATIC_THREAD_MGMT_SE3, compute_cu_en);
for (unsigned i = 0; i < 4; ++i)
si_pm4_set_reg(pm4, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 + i * 4,
i < sscreen->info.num_se ? compute_cu_en : 0x0);
si_pm4_set_reg(pm4, R_00B890_COMPUTE_USER_ACCUM_0, 0);
si_pm4_set_reg(pm4, R_00B894_COMPUTE_USER_ACCUM_1, 0);
@ -6286,10 +6285,9 @@ static void gfx10_init_gfx_preamble_state(struct si_context *sctx)
si_pm4_set_reg(pm4, R_00B89C_COMPUTE_USER_ACCUM_3, 0);
if (sctx->gfx_level >= GFX11) {
si_pm4_set_reg(pm4, R_00B8AC_COMPUTE_STATIC_THREAD_MGMT_SE4, compute_cu_en);
si_pm4_set_reg(pm4, R_00B8B0_COMPUTE_STATIC_THREAD_MGMT_SE5, compute_cu_en);
si_pm4_set_reg(pm4, R_00B8B4_COMPUTE_STATIC_THREAD_MGMT_SE6, compute_cu_en);
si_pm4_set_reg(pm4, R_00B8B8_COMPUTE_STATIC_THREAD_MGMT_SE7, compute_cu_en);
for (unsigned i = 4; i < 8; ++i)
si_pm4_set_reg(pm4, R_00B8AC_COMPUTE_STATIC_THREAD_MGMT_SE4 + (i - 4) * 4,
i < sscreen->info.num_se ? compute_cu_en : 0x0);
/* How many threads should go to 1 SE before moving onto the next. Think of GL1 cache hits.
* Only these values are valid: 0 (disabled), 64, 128, 256, 512