From 3f169d14d2d67339eb70b69477d8b35fc4bc4f5a Mon Sep 17 00:00:00 2001 From: David Rosca Date: Thu, 16 Oct 2025 14:58:17 +0200 Subject: [PATCH] radv/video: Fix AV1 bidir compound encode with order_hint disabled Cc: mesa-stable Reviewed-by: Benjamin Cheng (cherry picked from commit bcb6e6b6e6441f799099be43f579f23a164e2a08) Part-of: --- .pick_status.json | 2 +- src/amd/vulkan/radv_video_enc.c | 7 ++++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/.pick_status.json b/.pick_status.json index 458347247a7..1ae06636d02 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -1524,7 +1524,7 @@ "description": "radv/video: Fix AV1 bidir compound encode with order_hint disabled", "nominated": true, "nomination_type": 1, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": null, "notes": null diff --git a/src/amd/vulkan/radv_video_enc.c b/src/amd/vulkan/radv_video_enc.c index f6aac07e993..ef8a9f117ac 100644 --- a/src/amd/vulkan/radv_video_enc.c +++ b/src/amd/vulkan/radv_video_enc.c @@ -41,7 +41,7 @@ #define ENC_ALIGNMENT 256 #define RENCODE_V5_FW_INTERFACE_MAJOR_VERSION 1 -#define RENCODE_V5_FW_INTERFACE_MINOR_VERSION 3 +#define RENCODE_V5_FW_INTERFACE_MINOR_VERSION 10 #define RENCODE_V4_FW_INTERFACE_MAJOR_VERSION 1 #define RENCODE_V4_FW_INTERFACE_MINOR_VERSION 11 @@ -470,10 +470,10 @@ radv_enc_session_init(struct radv_cmd_buffer *cmd_buffer, const struct VkVideoEn if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_3) RADEON_ENC_CS(vid->enc_session.slice_output_enabled); RADEON_ENC_CS(vid->enc_session.display_remote); - if (pdev->enc_hw_ver == RADV_VIDEO_ENC_HW_4) { + if (pdev->enc_hw_ver == RADV_VIDEO_ENC_HW_4) RADEON_ENC_CS(vid->enc_session.WA_flags); + if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_4) RADEON_ENC_CS(0); - } RADEON_ENC_END(); } @@ -2247,6 +2247,7 @@ radv_enc_params_av1(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoK RADEON_ENC_CS(av1_picture_info->referenceNameSlotIndices[i]); RADEON_ENC_CS(slot_idx_0); RADEON_ENC_CS(slot_idx_1); + RADEON_ENC_CS(av1_picture_info->pStdPictureInfo->order_hint); RADEON_ENC_END(); }