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asahi: don't allocate varyings ourselves

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let the driver do it.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29179>
This commit is contained in:
Alyssa Rosenzweig 2024-04-19 22:07:02 -04:00 • committed by Marge Bot
parent 96521fbce3
commit 3eacd8a8b2
3 changed files with 31 additions and 28 deletions
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21
src/asahi/lib/agx_nir_lower_uvs.c
View file

@ -14,7 +14,6 @@
#include "nir_builder_opcodes.h"
#include "nir_intrinsics.h"
#include "nir_intrinsics_indices.h"
#include "pool.h"
#include "shader_enums.h"
struct ctx {
@ -253,26 +252,18 @@ agx_assign_uvs(struct agx_varyings_vs *varyings,
}
}
uint32_t
agx_link_varyings_vs_fs(struct agx_pool *pool, struct agx_varyings_vs *vs,
void
agx_link_varyings_vs_fs(void *out, struct agx_varyings_vs *vs,
unsigned nr_user_indices, struct agx_varyings_fs *fs,
bool first_provoking_vertex,
uint8_t sprite_coord_enable,
bool *generate_primitive_id)
{
assert(fs->nr_bindings > 0);
*generate_primitive_id = false;
/* If there are no bindings, there's nothing to emit */
if (fs->nr_bindings == 0)
return 0;
size_t linkage_size =
AGX_CF_BINDING_HEADER_LENGTH + (fs->nr_bindings * AGX_CF_BINDING_LENGTH);
struct agx_ptr t = agx_pool_alloc_aligned(pool, linkage_size, 256);
assert(t.gpu < (1ull << 32) && "varyings must be in low memory");
struct agx_cf_binding_header_packed *header = t.cpu;
struct agx_cf_binding_header_packed *header = out;
struct agx_cf_binding_packed *bindings = (void *)(header + 1);
unsigned user_base = 1 + (fs->reads_z ? 1 : 0);
@ -331,6 +322,4 @@ agx_link_varyings_vs_fs(struct agx_pool *pool, struct agx_varyings_vs *vs,
"overflowed coefficient registers");
}
}
return t.gpu;
}

11
src/asahi/lib/agx_uvs.h
View file

@ -81,10 +81,11 @@ void agx_assign_uvs(struct agx_varyings_vs *varyings,
struct agx_unlinked_uvs_layout *layout, uint64_t flat_mask,
uint64_t linear_mask);
struct agx_pool;
struct agx_varyings_fs;
uint32_t agx_link_varyings_vs_fs(
struct agx_pool *pool, struct agx_varyings_vs *vs, unsigned nr_user_indices,
struct agx_varyings_fs *fs, bool first_provoking_vertex,
uint8_t sprite_coord_enable, bool *generate_primitive_id);
void agx_link_varyings_vs_fs(void *out, struct agx_varyings_vs *vs,
unsigned nr_user_indices,
struct agx_varyings_fs *fs,
bool first_provoking_vertex,
uint8_t sprite_coord_enable,
bool *generate_primitive_id);

27
src/gallium/drivers/asahi/agx_state.c
View file

@ -3379,13 +3379,26 @@ agx_encode_state(struct agx_batch *batch, uint8_t *out)
if (IS_DIRTY(VS_PROG) || IS_DIRTY(FS_PROG) || IS_DIRTY(RS) ||
IS_DIRTY(PRIM)) {
batch->varyings = agx_link_varyings_vs_fs(
&batch->pipeline_pool, &batch->linked_varyings, vs->uvs.user_size,
&ctx->linked.fs->cf, ctx->rast->base.flatshade_first,
(batch->reduced_prim == MESA_PRIM_POINTS)
? ctx->rast->base.sprite_coord_enable
: 0,
&batch->generate_primitive_id);
unsigned bindings = ctx->linked.fs->cf.nr_bindings;
if (bindings) {
size_t linkage_size =
AGX_CF_BINDING_HEADER_LENGTH + (bindings * AGX_CF_BINDING_LENGTH);
struct agx_ptr t =
agx_pool_alloc_aligned(&batch->pipeline_pool, linkage_size, 16);
agx_link_varyings_vs_fs(t.cpu, &batch->linked_varyings,
vs->uvs.user_size, &ctx->linked.fs->cf,
ctx->rast->base.flatshade_first,
(batch->reduced_prim == MESA_PRIM_POINTS)
? ctx->rast->base.sprite_coord_enable
: 0,
&batch->generate_primitive_id);
batch->varyings = t.gpu;
} else {
batch->varyings = 0;
}
varyings_dirty = true;
ppp_updates++;