i965: add support for Intel 4 series chipsets

This commit is contained in:
Xiang, Haihao 2008-06-18 15:33:33 +08:00
parent 3064069540
commit 3e8aadee8b
2 changed files with 17 additions and 2 deletions

View file

@ -53,7 +53,11 @@
#define PCI_CHIP_I965_GM 0x2A02
#define PCI_CHIP_I965_GME 0x2A12
#define PCI_CHIP_IGD_GM 0x2A42
#define PCI_CHIP_IGD_GM 0x2A42
#define PCI_CHIP_IGD_E_G 0x2E02
#define PCI_CHIP_Q45_G 0x2E12
#define PCI_CHIP_G45_G 0x2E22
#define IS_MOBILE(devid) (devid == PCI_CHIP_I855_GM || \
devid == PCI_CHIP_I915_GM || \
@ -63,7 +67,11 @@
devid == PCI_CHIP_I965_GME || \
devid == PCI_CHIP_IGD_GM)
#define IS_IGD(devid) (devid == PCI_CHIP_IGD_GM)
#define IS_IGD_GM(devid) (devid == PCI_CHIP_IGD_GM)
#define IS_G4X(devid) (devid == PCI_CHIP_IGD_E_G || \
devid == PCI_CHIP_Q45_G || \
devid == PCI_CHIP_G45_G)
#define IS_IGD(devid) (IS_IGD_GM(devid) || IS_G4X(devid))
#define IS_915(devid) (devid == PCI_CHIP_I915_G || \
devid == PCI_CHIP_E7221_G || \

View file

@ -167,8 +167,15 @@ intelGetString(GLcontext * ctx, GLenum name)
chipset = "Intel(R) 965GME/GLE";
break;
case PCI_CHIP_IGD_GM:
case PCI_CHIP_IGD_E_G:
chipset = "Intel(R) Integrated Graphics Device";
break;
case PCI_CHIP_G45_G:
chipset = "Intel(R) G45/G43";
break;
case PCI_CHIP_Q45_G:
chipset = "Intel(R) Q45/Q43";
break;
default:
chipset = "Unknown Intel Chipset";
break;