diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index d4f5fdf439a..a0d356d5d21 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -37,16 +37,7 @@
 
 #include "ds/intel_tracepoints.h"
 
-/* We reserve :
- *    - GPR 14 for secondary command buffer returns
- *    - GPR 15 for conditional rendering
- */
-#define MI_BUILDER_NUM_ALLOC_GPRS 14
-#define __gen_get_batch_dwords anv_batch_emit_dwords
-#define __gen_address_offset anv_address_add
-#define __gen_get_batch_address(b, a) anv_batch_address(b, a)
-#include "common/mi_builder.h"
-
+#include "genX_mi_builder.h"
 #include "genX_cmd_draw_generated_flush.h"
 
 static void genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
diff --git a/src/intel/vulkan/genX_cmd_compute.c b/src/intel/vulkan/genX_cmd_compute.c
index 4721277b0af..e6668228aac 100644
--- a/src/intel/vulkan/genX_cmd_compute.c
+++ b/src/intel/vulkan/genX_cmd_compute.c
@@ -38,15 +38,7 @@
 
 #include "ds/intel_tracepoints.h"
 
-/* We reserve :
- *    - GPR 14 for secondary command buffer returns
- *    - GPR 15 for conditional rendering
- */
-#define MI_BUILDER_NUM_ALLOC_GPRS 14
-#define __gen_get_batch_dwords anv_batch_emit_dwords
-#define __gen_address_offset anv_address_add
-#define __gen_get_batch_address(b, a) anv_batch_address(b, a)
-#include "common/mi_builder.h"
+#include "genX_mi_builder.h"
 
 void
 genX(cmd_buffer_ensure_cfe_state)(struct anv_cmd_buffer *cmd_buffer,
diff --git a/src/intel/vulkan/genX_cmd_draw.c b/src/intel/vulkan/genX_cmd_draw.c
index 2d4cc2f3fd4..bc0b0d23d9d 100644
--- a/src/intel/vulkan/genX_cmd_draw.c
+++ b/src/intel/vulkan/genX_cmd_draw.c
@@ -37,15 +37,7 @@
 
 #include "ds/intel_tracepoints.h"
 
-/* We reserve :
- *    - GPR 14 for secondary command buffer returns
- *    - GPR 15 for conditional rendering
- */
-#define MI_BUILDER_NUM_ALLOC_GPRS 14
-#define __gen_get_batch_dwords anv_batch_emit_dwords
-#define __gen_address_offset anv_address_add
-#define __gen_get_batch_address(b, a) anv_batch_address(b, a)
-#include "common/mi_builder.h"
+#include "genX_mi_builder.h"
 
 static void
 cmd_buffer_alloc_gfx_push_constants(struct anv_cmd_buffer *cmd_buffer)
diff --git a/src/intel/vulkan/genX_mi_builder.h b/src/intel/vulkan/genX_mi_builder.h
new file mode 100644
index 00000000000..33b4e821344
--- /dev/null
+++ b/src/intel/vulkan/genX_mi_builder.h
@@ -0,0 +1,19 @@
+/* Copyright © 2024 Intel Corporation
+ * SPDX-License-Identifier: MIT
+ */
+
+#pragma once
+
+#include "genxml/gen_macros.h"
+#include "genxml/genX_pack.h"
+
+/* We reserve :
+ *    - GPR 14 for perf queries
+ *    - GPR 15 for conditional rendering
+ */
+#define MI_BUILDER_NUM_ALLOC_GPRS 14
+#define MI_BUILDER_CAN_WRITE_BATCH true
+#define __gen_get_batch_dwords anv_batch_emit_dwords
+#define __gen_address_offset anv_address_add
+#define __gen_get_batch_address(b, a) anv_batch_address(b, a)
+#include "common/mi_builder.h"
diff --git a/src/intel/vulkan/genX_query.c b/src/intel/vulkan/genX_query.c
index 18bc4d30ba2..5aeb27bedae 100644
--- a/src/intel/vulkan/genX_query.c
+++ b/src/intel/vulkan/genX_query.c
@@ -37,16 +37,7 @@
 #include "ds/intel_tracepoints.h"
 
 #include "anv_internal_kernels.h"
-
-/* We reserve :
- *    - GPR 14 for perf queries
- *    - GPR 15 for conditional rendering
- */
-#define MI_BUILDER_NUM_ALLOC_GPRS 14
-#define MI_BUILDER_CAN_WRITE_BATCH true
-#define __gen_get_batch_dwords anv_batch_emit_dwords
-#define __gen_address_offset anv_address_add
-#define __gen_get_batch_address(b, a) anv_batch_address(b, a)
+#include "genX_mi_builder.h"
 
 #if GFX_VERx10 >= 125
 #define ANV_PIPELINE_STATISTICS_MASK 0x00001fff
@@ -54,7 +45,6 @@
 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
 #endif
 
-#include "common/mi_builder.h"
 #include "perf/intel_perf.h"
 #include "perf/intel_perf_mdapi.h"
 #include "perf/intel_perf_regs.h"
diff --git a/src/intel/vulkan/grl/grl_metakernel_gen.py b/src/intel/vulkan/grl/grl_metakernel_gen.py
index 6c416bd3d5d..9e09df8a96d 100644
--- a/src/intel/vulkan/grl/grl_metakernel_gen.py
+++ b/src/intel/vulkan/grl/grl_metakernel_gen.py
@@ -871,15 +871,7 @@ C_PROLOGUE = COPYRIGHT + '''
 #include "genxml/genX_pack.h"
 #include "genxml/genX_rt_pack.h"
 
-/* We reserve :
- *    - GPR 14 for secondary command buffer returns
- *    - GPR 15 for conditional rendering
- */
-#define MI_BUILDER_NUM_ALLOC_GPRS 14
-#define __gen_get_batch_dwords anv_batch_emit_dwords
-#define __gen_address_offset anv_address_add
-#define __gen_get_batch_address(b, a) anv_batch_address(b, a)
-#include "common/mi_builder.h"
+#include "genX_mi_builder.h"
 
 #define MI_PREDICATE_RESULT mi_reg32(0x2418)
 #define DISPATCHDIM_X mi_reg32(0x2500)