diff --git a/src/amd/compiler/instruction_selection/aco_isel_setup.cpp b/src/amd/compiler/instruction_selection/aco_isel_setup.cpp
index 942be54400b..63a20cdd67a 100644
--- a/src/amd/compiler/instruction_selection/aco_isel_setup.cpp
+++ b/src/amd/compiler/instruction_selection/aco_isel_setup.cpp
@@ -450,6 +450,7 @@ init_context(isel_context* ctx, nir_shader* shader)
                case nir_op_e4m3fn2f:
                case nir_op_e5m22f:
                case nir_op_fmulz:
+               case nir_op_ffmaz:
                case nir_op_ffmaz_old:
                case nir_op_f2f64:
                case nir_op_u2f64:
@@ -485,6 +486,7 @@ init_context(isel_context* ctx, nir_shader* shader)
                case nir_op_f2f16_ru:
                case nir_op_f2f16_rd: type = RegType::vgpr; break;
                case nir_op_fmul:
+               case nir_op_ffma:
                case nir_op_ffma_old:
                case nir_op_fadd:
                case nir_op_fsub:
diff --git a/src/amd/compiler/instruction_selection/aco_select_nir_alu.cpp b/src/amd/compiler/instruction_selection/aco_select_nir_alu.cpp
index 3527d2cd262..8195f0fc3ec 100644
--- a/src/amd/compiler/instruction_selection/aco_select_nir_alu.cpp
+++ b/src/amd/compiler/instruction_selection/aco_select_nir_alu.cpp
@@ -1925,6 +1925,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr)
       }
       break;
    }
+   case nir_op_ffma:
    case nir_op_ffma_old: {
       if (dst.regClass() == v2b) {
          emit_vop3a_instruction(ctx, instr, aco_opcode::v_fma_f16, dst, false, 3);
@@ -1961,6 +1962,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr)
       }
       break;
    }
+   case nir_op_ffmaz:
    case nir_op_ffmaz_old: {
       if (dst.regClass() == v1) {
          emit_vop3a_instruction(ctx, instr, aco_opcode::v_fma_legacy_f32, dst,