diff --git a/.pick_status.json b/.pick_status.json
index e12325320e6..44ccaeff8dd 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -229,7 +229,7 @@
         "description": "ac/nir: Store only lowest 8 bits for task draw ring DWORD3.",
         "nominated": true,
         "nomination_type": 0,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": null
     },
diff --git a/src/amd/common/ac_nir_lower_taskmesh_io_to_mem.c b/src/amd/common/ac_nir_lower_taskmesh_io_to_mem.c
index a0584abba23..5f320c5a77d 100644
--- a/src/amd/common/ac_nir_lower_taskmesh_io_to_mem.c
+++ b/src/amd/common/ac_nir_lower_taskmesh_io_to_mem.c
@@ -211,7 +211,7 @@ task_draw_ready_bit(nir_builder *b,
    nir_ssa_def *workgroup_index = task_workgroup_index(b, s);
 
    nir_ssa_def *idx = nir_iadd_nuw(b, ring_entry, workgroup_index);
-   return nir_ubfe(b, idx, nir_imm_int(b, util_bitcount(s->num_entries - 1)), nir_imm_int(b, 1));
+   return nir_u2u8(b, nir_ubfe(b, idx, nir_imm_int(b, util_bitcount(s->num_entries - 1)), nir_imm_int(b, 1)));
 }
 
 static nir_ssa_def *
@@ -288,9 +288,13 @@ lower_task_launch_mesh_workgroups(nir_builder *b,
       nir_ssa_def *x = nir_channel(b, dimensions, 0);
       nir_ssa_def *y = nir_channel(b, dimensions, 1);
       nir_ssa_def *z = nir_channel(b, dimensions, 2);
-      nir_ssa_def *rdy = task_draw_ready_bit(b, s);
-      nir_ssa_def *store_val = nir_vec4(b, x, y, z, rdy);
-      task_write_draw_ring(b, store_val, 0, s);
+
+      /* Dispatch dimensions of mesh shader workgroups. */
+      task_write_draw_ring(b, nir_vec3(b, x, y, z), 0, s);
+      /* Prevent the two stores from being reordered. */
+      nir_scoped_memory_barrier(b, NIR_SCOPE_INVOCATION, NIR_MEMORY_RELEASE, nir_var_shader_out);
+      /* Ready bit, only write the low 8 bits. */
+      task_write_draw_ring(b, task_draw_ready_bit(b, s), 12, s);
    }
    nir_pop_if(b, if_invocation_index_zero);