mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-05-09 04:38:03 +02:00
Merge branch 'r300-vertprog-branch' of ssh://people.freedesktop.org/~z3ro/mesa
This commit is contained in:
Oliver McFadden
commit
3e0797f3b7
7 changed files with 816 additions and 973 deletions
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@ -96,6 +96,66 @@ typedef struct r300_fragment_program_swizzle {
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#define DRI_CONF_FP_OPTIMIZATION_SPEED 0
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#define DRI_CONF_FP_OPTIMIZATION_QUALITY 1
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#if 1
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/**
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* Fragment program helper macros
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*/
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/* Produce unshifted source selectors */
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#define FP_TMP(idx) (idx)
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#define FP_CONST(idx) ((idx) | (1 << 5))
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/* Produce source/dest selector dword */
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#define FP_SELC_MASK_NO 0
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#define FP_SELC_MASK_X 1
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#define FP_SELC_MASK_Y 2
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#define FP_SELC_MASK_XY 3
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#define FP_SELC_MASK_Z 4
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#define FP_SELC_MASK_XZ 5
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#define FP_SELC_MASK_YZ 6
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#define FP_SELC_MASK_XYZ 7
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#define FP_SELC(destidx,regmask,outmask,src0,src1,src2) \
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(((destidx) << R300_FPI1_DSTC_SHIFT) | \
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(FP_SELC_MASK_##regmask << 23) | \
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(FP_SELC_MASK_##outmask << 26) | \
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((src0) << R300_FPI1_SRC0C_SHIFT) | \
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((src1) << R300_FPI1_SRC1C_SHIFT) | \
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((src2) << R300_FPI1_SRC2C_SHIFT))
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#define FP_SELA_MASK_NO 0
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#define FP_SELA_MASK_W 1
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#define FP_SELA(destidx,regmask,outmask,src0,src1,src2) \
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(((destidx) << R300_FPI3_DSTA_SHIFT) | \
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(FP_SELA_MASK_##regmask << 23) | \
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(FP_SELA_MASK_##outmask << 24) | \
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((src0) << R300_FPI3_SRC0A_SHIFT) | \
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((src1) << R300_FPI3_SRC1A_SHIFT) | \
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((src2) << R300_FPI3_SRC2A_SHIFT))
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/* Produce unshifted argument selectors */
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#define FP_ARGC(source) R300_FPI0_ARGC_##source
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#define FP_ARGA(source) R300_FPI2_ARGA_##source
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#define FP_ABS(arg) ((arg) | (1 << 6))
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#define FP_NEG(arg) ((arg) ^ (1 << 5))
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/* Produce instruction dword */
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#define FP_INSTRC(opcode,arg0,arg1,arg2) \
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(R300_FPI0_OUTC_##opcode | \
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((arg0) << R300_FPI0_ARG0C_SHIFT) | \
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((arg1) << R300_FPI0_ARG1C_SHIFT) | \
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((arg2) << R300_FPI0_ARG2C_SHIFT))
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#define FP_INSTRA(opcode,arg0,arg1,arg2) \
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(R300_FPI2_OUTA_##opcode | \
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((arg0) << R300_FPI2_ARG0A_SHIFT) | \
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((arg1) << R300_FPI2_ARG1A_SHIFT) | \
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((arg2) << R300_FPI2_ARG2A_SHIFT))
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#endif
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struct r300_fragment_program;
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extern void r300TranslateFragmentShader(r300ContextPtr r300,
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@ -51,7 +51,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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#include "r300_ioctl.h"
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#include "r300_cmdbuf.h"
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#include "r300_state.h"
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#include "r300_program.h"
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#include "r300_vertprog.h"
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#include "radeon_reg.h"
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#include "r300_emit.h"
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@ -318,6 +318,7 @@ static void r300EmitClearState(GLcontext * ctx)
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if (has_tcl) {
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R300_STATECHANGE(r300, pvs);
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reg_start(R300_VAP_PVS_CNTL_1, 2);
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e32((0 << R300_PVS_CNTL_1_PROGRAM_START_SHIFT) |
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(0 << R300_PVS_CNTL_1_POS_END_SHIFT) |
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(1 << R300_PVS_CNTL_1_PROGRAM_END_SHIFT));
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@ -326,14 +327,15 @@ static void r300EmitClearState(GLcontext * ctx)
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R300_STATECHANGE(r300, vpi);
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vsf_start_fragment(0x0, 8);
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e32(VP_OUT(ADD, OUT, 0, XYZW));
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e32(VP_IN(IN, 0));
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e32(VP_ZERO());
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e32(PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE, 0, 0xf, PVS_DST_REG_OUT));
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e32(PVS_SRC_OPERAND(0, PVS_SRC_SELECT_X, PVS_SRC_SELECT_Y, PVS_SRC_SELECT_Z, PVS_SRC_SELECT_W, PVS_SRC_REG_INPUT, VSF_FLAG_NONE));
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e32(PVS_SRC_OPERAND(0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_REG_INPUT, VSF_FLAG_NONE));
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e32(0x0);
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e32(VP_OUT(ADD, OUT, 1, XYZW));
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e32(VP_IN(IN, 1));
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e32(VP_ZERO());
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e32(PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE, 1, 0xf, PVS_DST_REG_OUT));
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e32(PVS_SRC_OPERAND(1, PVS_SRC_SELECT_X, PVS_SRC_SELECT_Y, PVS_SRC_SELECT_Z, PVS_SRC_SELECT_W, PVS_SRC_REG_INPUT, VSF_FLAG_NONE));
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e32(PVS_SRC_OPERAND(1, PVS_SRC_SELECT_FORCE_0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_REG_INPUT, VSF_FLAG_NONE));
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e32(0x0);
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}
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}
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@ -1,150 +0,0 @@
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/*
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Copyright (C) 2004 Nicolai Haehnle. All Rights Reserved.
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice (including the
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next paragraph) shall be included in all copies or substantial
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portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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**************************************************************************/
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/*
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* Authors:
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* Nicolai Haehnle <prefect_@gmx.net>
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*/
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#ifndef __R300_PROGRAM_H__
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#define __R300_PROGRAM_H__
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#include "r300_reg.h"
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/**
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* Vertex program helper macros
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*/
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/* Produce out dword */
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#define VP_OUTCLASS_TMP R300_VPI_OUT_REG_CLASS_TEMPORARY
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#define VP_OUTCLASS_OUT R300_VPI_OUT_REG_CLASS_RESULT
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#define VP_OUTMASK_X R300_VPI_OUT_WRITE_X
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#define VP_OUTMASK_Y R300_VPI_OUT_WRITE_Y
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#define VP_OUTMASK_Z R300_VPI_OUT_WRITE_Z
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#define VP_OUTMASK_W R300_VPI_OUT_WRITE_W
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#define VP_OUTMASK_XY (VP_OUTMASK_X|VP_OUTMASK_Y)
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#define VP_OUTMASK_XZ (VP_OUTMASK_X|VP_OUTMASK_Z)
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#define VP_OUTMASK_XW (VP_OUTMASK_X|VP_OUTMASK_W)
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#define VP_OUTMASK_XYZ (VP_OUTMASK_XY|VP_OUTMASK_Z)
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#define VP_OUTMASK_XYW (VP_OUTMASK_XY|VP_OUTMASK_W)
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#define VP_OUTMASK_XZW (VP_OUTMASK_XZ|VP_OUTMASK_W)
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#define VP_OUTMASK_XYZW (VP_OUTMASK_XYZ|VP_OUTMASK_W)
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#define VP_OUTMASK_YZ (VP_OUTMASK_Y|VP_OUTMASK_Z)
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#define VP_OUTMASK_YW (VP_OUTMASK_Y|VP_OUTMASK_W)
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#define VP_OUTMASK_YZW (VP_OUTMASK_YZ|VP_OUTMASK_W)
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#define VP_OUTMASK_ZW (VP_OUTMASK_Z|VP_OUTMASK_W)
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#define VP_OUT(instr,outclass,outidx,outmask) \
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(R300_VPI_OUT_OP_##instr | \
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((outidx) << R300_VPI_OUT_REG_INDEX_SHIFT) | \
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VP_OUTCLASS_##outclass | \
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VP_OUTMASK_##outmask)
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/* Produce in dword */
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#define VP_INCLASS_TMP R300_VPI_IN_REG_CLASS_TEMPORARY
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#define VP_INCLASS_IN R300_VPI_IN_REG_CLASS_ATTRIBUTE
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#define VP_INCLASS_CONST R300_VPI_IN_REG_CLASS_PARAMETER
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#define VP_IN(class,idx) \
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(((idx) << R300_VPI_IN_REG_INDEX_SHIFT) | \
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VP_INCLASS_##class | \
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(R300_VPI_IN_SELECT_X << R300_VPI_IN_X_SHIFT) | \
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(R300_VPI_IN_SELECT_Y << R300_VPI_IN_Y_SHIFT) | \
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(R300_VPI_IN_SELECT_Z << R300_VPI_IN_Z_SHIFT) | \
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(R300_VPI_IN_SELECT_W << R300_VPI_IN_W_SHIFT))
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#define VP_ZERO() \
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((R300_VPI_IN_SELECT_ZERO << R300_VPI_IN_X_SHIFT) | \
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(R300_VPI_IN_SELECT_ZERO << R300_VPI_IN_Y_SHIFT) | \
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(R300_VPI_IN_SELECT_ZERO << R300_VPI_IN_Z_SHIFT) | \
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(R300_VPI_IN_SELECT_ZERO << R300_VPI_IN_W_SHIFT))
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#define VP_ONE() \
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((R300_VPI_IN_SELECT_ONE << R300_VPI_IN_X_SHIFT) | \
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(R300_VPI_IN_SELECT_ONE << R300_VPI_IN_Y_SHIFT) | \
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(R300_VPI_IN_SELECT_ONE << R300_VPI_IN_Z_SHIFT) | \
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(R300_VPI_IN_SELECT_ONE << R300_VPI_IN_W_SHIFT))
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#define VP_NEG(in,comp) ((in) ^ (R300_VPI_IN_NEG_##comp))
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#define VP_NEGALL(in,comp) VP_NEG(VP_NEG(VP_NEG(VP_NEG((in),X),Y),Z),W)
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/**
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* Fragment program helper macros
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*/
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/* Produce unshifted source selectors */
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#define FP_TMP(idx) (idx)
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#define FP_CONST(idx) ((idx) | (1 << 5))
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/* Produce source/dest selector dword */
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#define FP_SELC_MASK_NO 0
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#define FP_SELC_MASK_X 1
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#define FP_SELC_MASK_Y 2
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#define FP_SELC_MASK_XY 3
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#define FP_SELC_MASK_Z 4
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#define FP_SELC_MASK_XZ 5
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#define FP_SELC_MASK_YZ 6
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#define FP_SELC_MASK_XYZ 7
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#define FP_SELC(destidx,regmask,outmask,src0,src1,src2) \
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(((destidx) << R300_FPI1_DSTC_SHIFT) | \
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(FP_SELC_MASK_##regmask << 23) | \
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(FP_SELC_MASK_##outmask << 26) | \
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((src0) << R300_FPI1_SRC0C_SHIFT) | \
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((src1) << R300_FPI1_SRC1C_SHIFT) | \
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((src2) << R300_FPI1_SRC2C_SHIFT))
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#define FP_SELA_MASK_NO 0
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#define FP_SELA_MASK_W 1
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#define FP_SELA(destidx,regmask,outmask,src0,src1,src2) \
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(((destidx) << R300_FPI3_DSTA_SHIFT) | \
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(FP_SELA_MASK_##regmask << 23) | \
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(FP_SELA_MASK_##outmask << 24) | \
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((src0) << R300_FPI3_SRC0A_SHIFT) | \
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((src1) << R300_FPI3_SRC1A_SHIFT) | \
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((src2) << R300_FPI3_SRC2A_SHIFT))
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/* Produce unshifted argument selectors */
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#define FP_ARGC(source) R300_FPI0_ARGC_##source
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#define FP_ARGA(source) R300_FPI2_ARGA_##source
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#define FP_ABS(arg) ((arg) | (1 << 6))
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#define FP_NEG(arg) ((arg) ^ (1 << 5))
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/* Produce instruction dword */
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#define FP_INSTRC(opcode,arg0,arg1,arg2) \
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(R300_FPI0_OUTC_##opcode | \
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((arg0) << R300_FPI0_ARG0C_SHIFT) | \
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((arg1) << R300_FPI0_ARG1C_SHIFT) | \
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((arg2) << R300_FPI0_ARG2C_SHIFT))
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#define FP_INSTRA(opcode,arg0,arg1,arg2) \
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(R300_FPI2_OUTA_##opcode | \
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((arg0) << R300_FPI2_ARG0A_SHIFT) | \
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((arg1) << R300_FPI2_ARG1A_SHIFT) | \
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((arg2) << R300_FPI2_ARG2A_SHIFT))
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extern void debug_vp(GLcontext * ctx, struct gl_vertex_program *vp);
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#endif /* __R300_PROGRAM_H__ */
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@ -2383,115 +2383,189 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
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# define ZB_STENCILREFMASK_BF_STENCILWRITEMASK_SHIFT 16
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# define ZB_STENCILREFMASK_BF_STENCILWRITEMASK_MASK 0xffff0000
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/* BEGIN: Vertex program instruction set */
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/* Every instruction is four dwords long:
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* DWORD 0: output and opcode
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* DWORD 1: first argument
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* DWORD 2: second argument
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* DWORD 3: third argument
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/**
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* \defgroup R3XX_R5XX_PROGRAMMABLE_VERTEX_SHADER_DESCRIPTION R3XX-R5XX PROGRAMMABLE VERTEX SHADER DESCRIPTION
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*
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* Notes:
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* - ABS r, a is implemented as MAX r, a, -a
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* - MOV is implemented as ADD to zero
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* - XPD is implemented as MUL + MAD
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* - FLR is implemented as FRC + ADD
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* - apparently, fglrx tries to schedule instructions so that there is at
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* least one instruction between the write to a temporary and the first
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* read from said temporary; however, violations of this scheduling are
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* allowed
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* - register indices seem to be unrelated with OpenGL aliasing to
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* conventional state
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* - only one attribute and one parameter can be loaded at a time; however,
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* the same attribute/parameter can be used for more than one argument
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* - the second software argument for POW is the third hardware argument
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* (no idea why)
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* - MAD with only temporaries as input seems to use VPI_OUT_SELECT_MAD_2
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*
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* There is some magic surrounding LIT:
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* The single argument is replicated across all three inputs, but swizzled:
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* First argument: xyzy
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* Second argument: xyzx
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* Third argument: xyzw
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* Whenever the result is used later in the fragment program, fglrx forces
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* x and w to be 1.0 in the input selection; I don't know whether this is
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* strictly necessary
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* The PVS_DST_MATH_INST is used to identify whether the instruction is a Vector
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* Engine instruction or a Math Engine instruction.
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*/
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#define R300_VPI_OUT_OP_DOT (1 << 0)
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#define R300_VPI_OUT_OP_MUL (2 << 0)
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#define R300_VPI_OUT_OP_ADD (3 << 0)
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#define R300_VPI_OUT_OP_MAD (4 << 0)
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#define R300_VPI_OUT_OP_DST (5 << 0)
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#define R300_VPI_OUT_OP_FRC (6 << 0)
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#define R300_VPI_OUT_OP_MAX (7 << 0)
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#define R300_VPI_OUT_OP_MIN (8 << 0)
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#define R300_VPI_OUT_OP_SGE (9 << 0)
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#define R300_VPI_OUT_OP_SLT (10 << 0)
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/* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, vector(scalar, vector) */
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#define R300_VPI_OUT_OP_UNK12 (12 << 0)
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#define R300_VPI_OUT_OP_ARL (13 << 0)
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#define R300_VPI_OUT_OP_EXP (65 << 0)
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#define R300_VPI_OUT_OP_LOG (66 << 0)
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/* Used in fog computations, scalar(scalar) */
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#define R300_VPI_OUT_OP_UNK67 (67 << 0)
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#define R300_VPI_OUT_OP_LIT (68 << 0)
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#define R300_VPI_OUT_OP_POW (69 << 0)
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#define R300_VPI_OUT_OP_RCP (70 << 0)
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#define R300_VPI_OUT_OP_RSQ (72 << 0)
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/* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, scalar(scalar) */
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#define R300_VPI_OUT_OP_UNK73 (73 << 0)
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#define R300_VPI_OUT_OP_EX2 (75 << 0)
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#define R300_VPI_OUT_OP_LG2 (76 << 0)
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#define R300_VPI_OUT_OP_MAD_2 (128 << 0)
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/* all temps, vector(scalar, vector, vector) */
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#define R300_VPI_OUT_OP_UNK129 (129 << 0)
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#define R300_VPI_OUT_REG_CLASS_TEMPORARY (0 << 8)
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#define R300_VPI_OUT_REG_CLASS_ADDR (1 << 8)
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#define R300_VPI_OUT_REG_CLASS_RESULT (2 << 8)
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#define R300_VPI_OUT_REG_CLASS_MASK (31 << 8)
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/*\{*/
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#define R300_VPI_OUT_REG_INDEX_SHIFT 13
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/* GUESS based on fglrx native limits */
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#define R300_VPI_OUT_REG_INDEX_MASK (31 << 13)
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enum {
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/* R3XX */
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VECTOR_NO_OP = 0,
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VE_DOT_PRODUCT = 1,
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VE_MULTIPLY = 2,
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VE_ADD = 3,
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VE_MULTIPLY_ADD = 4,
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VE_DISTANCE_VECTOR = 5,
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VE_FRACTION = 6,
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VE_MAXIMUM = 7,
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VE_MINIMUM = 8,
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VE_SET_GREATER_THAN_EQUAL = 9,
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VE_SET_LESS_THAN = 10,
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VE_MULTIPLYX2_ADD = 11,
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VE_MULTIPLY_CLAMP = 12,
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VE_FLT2FIX_DX = 13,
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VE_FLT2FIX_DX_RND = 14,
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/* R5XX */
|
||||
VE_PRED_SET_EQ_PUSH = 15,
|
||||
VE_PRED_SET_GT_PUSH = 16,
|
||||
VE_PRED_SET_GTE_PUSH = 17,
|
||||
VE_PRED_SET_NEQ_PUSH = 18,
|
||||
VE_COND_WRITE_EQ = 19,
|
||||
VE_COND_WRITE_GT = 20,
|
||||
VE_COND_WRITE_GTE = 21,
|
||||
VE_COND_WRITE_NEQ = 22,
|
||||
VE_COND_MUX_EQ = 23,
|
||||
VE_COND_MUX_GT = 24,
|
||||
VE_COND_MUX_GTE = 25,
|
||||
VE_SET_GREATER_THAN = 26,
|
||||
VE_SET_EQUAL = 27,
|
||||
VE_SET_NOT_EQUAL = 28,
|
||||
};
|
||||
|
||||
#define R300_VPI_OUT_WRITE_X (1 << 20)
|
||||
#define R300_VPI_OUT_WRITE_Y (1 << 21)
|
||||
#define R300_VPI_OUT_WRITE_Z (1 << 22)
|
||||
#define R300_VPI_OUT_WRITE_W (1 << 23)
|
||||
enum {
|
||||
/* R3XX */
|
||||
MATH_NO_OP = 0,
|
||||
ME_EXP_BASE2_DX = 1,
|
||||
ME_LOG_BASE2_DX = 2,
|
||||
ME_EXP_BASEE_FF = 3,
|
||||
ME_LIGHT_COEFF_DX = 4,
|
||||
ME_POWER_FUNC_FF = 5,
|
||||
ME_RECIP_DX = 6,
|
||||
ME_RECIP_FF = 7,
|
||||
ME_RECIP_SQRT_DX = 8,
|
||||
ME_RECIP_SQRT_FF = 9,
|
||||
ME_MULTIPLY = 10,
|
||||
ME_EXP_BASE2_FULL_DX = 11,
|
||||
ME_LOG_BASE2_FULL_DX = 12,
|
||||
ME_POWER_FUNC_FF_CLAMP_B = 13,
|
||||
ME_POWER_FUNC_FF_CLAMP_B1 = 14,
|
||||
ME_POWER_FUNC_FF_CLAMP_01 = 15,
|
||||
ME_SIN = 16,
|
||||
ME_COS = 17,
|
||||
/* R5XX */
|
||||
ME_LOG_BASE2_IEEE = 18,
|
||||
ME_RECIP_IEEE = 19,
|
||||
ME_RECIP_SQRT_IEEE = 20,
|
||||
ME_PRED_SET_EQ = 21,
|
||||
ME_PRED_SET_GT = 22,
|
||||
ME_PRED_SET_GTE = 23,
|
||||
ME_PRED_SET_NEQ = 24,
|
||||
ME_PRED_SET_CLR = 25,
|
||||
ME_PRED_SET_INV = 26,
|
||||
ME_PRED_SET_POP = 27,
|
||||
ME_PRED_SET_RESTORE = 28,
|
||||
};
|
||||
|
||||
#define R300_VPI_IN_REG_CLASS_TEMPORARY (0 << 0)
|
||||
#define R300_VPI_IN_REG_CLASS_ATTRIBUTE (1 << 0)
|
||||
#define R300_VPI_IN_REG_CLASS_PARAMETER (2 << 0)
|
||||
#define R300_VPI_IN_REG_CLASS_NONE (9 << 0)
|
||||
#define R300_VPI_IN_REG_CLASS_MASK (31 << 0)
|
||||
enum {
|
||||
/* R3XX */
|
||||
PVS_MACRO_OP_2CLK_MADD = 0,
|
||||
PVS_MACRO_OP_2CLK_M2X_ADD = 1,
|
||||
};
|
||||
|
||||
#define R300_VPI_IN_REG_INDEX_SHIFT 5
|
||||
/* GUESS based on fglrx native limits */
|
||||
#define R300_VPI_IN_REG_INDEX_MASK (255 << 5)
|
||||
enum {
|
||||
PVS_SRC_REG_TEMPORARY = 0, /* Intermediate Storage */
|
||||
PVS_SRC_REG_INPUT = 1, /* Input Vertex Storage */
|
||||
PVS_SRC_REG_CONSTANT = 2, /* Constant State Storage */
|
||||
PVS_SRC_REG_ALT_TEMPORARY = 3, /* Alternate Intermediate Storage */
|
||||
};
|
||||
|
||||
/* The R300 can select components from the input register arbitrarily.
|
||||
* Use the following constants, shifted by the component shift you
|
||||
* want to select
|
||||
*/
|
||||
#define R300_VPI_IN_SELECT_X 0
|
||||
#define R300_VPI_IN_SELECT_Y 1
|
||||
#define R300_VPI_IN_SELECT_Z 2
|
||||
#define R300_VPI_IN_SELECT_W 3
|
||||
#define R300_VPI_IN_SELECT_ZERO 4
|
||||
#define R300_VPI_IN_SELECT_ONE 5
|
||||
#define R300_VPI_IN_SELECT_MASK 7
|
||||
enum {
|
||||
PVS_DST_REG_TEMPORARY = 0, /* Intermediate Storage */
|
||||
PVS_DST_REG_A0 = 1, /* Address Register Storage */
|
||||
PVS_DST_REG_OUT = 2, /* Output Memory. Used for all outputs */
|
||||
PVS_DST_REG_OUT_REPL_X = 3, /* Output Memory & Replicate X to all channels */
|
||||
PVS_DST_REG_ALT_TEMPORARY = 4, /* Alternate Intermediate Storage */
|
||||
PVS_DST_REG_INPUT = 5, /* Output Memory & Replicate X to all channels */
|
||||
};
|
||||
|
||||
#define R300_VPI_IN_X_SHIFT 13
|
||||
#define R300_VPI_IN_Y_SHIFT 16
|
||||
#define R300_VPI_IN_Z_SHIFT 19
|
||||
#define R300_VPI_IN_W_SHIFT 22
|
||||
enum {
|
||||
PVS_SRC_SELECT_X = 0, /* Select X Component */
|
||||
PVS_SRC_SELECT_Y = 1, /* Select Y Component */
|
||||
PVS_SRC_SELECT_Z = 2, /* Select Z Component */
|
||||
PVS_SRC_SELECT_W = 3, /* Select W Component */
|
||||
PVS_SRC_SELECT_FORCE_0 = 4, /* Force Component to 0.0 */
|
||||
PVS_SRC_SELECT_FORCE_1 = 5, /* Force Component to 1.0 */
|
||||
};
|
||||
|
||||
#define R300_VPI_IN_NEG_X (1 << 25)
|
||||
#define R300_VPI_IN_NEG_Y (1 << 26)
|
||||
#define R300_VPI_IN_NEG_Z (1 << 27)
|
||||
#define R300_VPI_IN_NEG_W (1 << 28)
|
||||
/* END: Vertex program instruction set */
|
||||
/* PVS Opcode & Destination Operand Description */
|
||||
|
||||
enum {
|
||||
PVS_DST_OPCODE_MASK = 0x3f,
|
||||
PVS_DST_OPCODE_SHIFT = 0,
|
||||
PVS_DST_MATH_INST_MASK = 0x1,
|
||||
PVS_DST_MATH_INST_SHIFT = 6,
|
||||
PVS_DST_MACRO_INST_MASK = 0x1,
|
||||
PVS_DST_MACRO_INST_SHIFT = 7,
|
||||
PVS_DST_REG_TYPE_MASK = 0xf,
|
||||
PVS_DST_REG_TYPE_SHIFT = 8,
|
||||
PVS_DST_ADDR_MODE_1_MASK = 0x1,
|
||||
PVS_DST_ADDR_MODE_1_SHIFT = 12,
|
||||
PVS_DST_OFFSET_MASK = 0x7f,
|
||||
PVS_DST_OFFSET_SHIFT = 13,
|
||||
PVS_DST_WE_X_MASK = 0x1,
|
||||
PVS_DST_WE_X_SHIFT = 20,
|
||||
PVS_DST_WE_Y_MASK = 0x1,
|
||||
PVS_DST_WE_Y_SHIFT = 21,
|
||||
PVS_DST_WE_Z_MASK = 0x1,
|
||||
PVS_DST_WE_Z_SHIFT = 22,
|
||||
PVS_DST_WE_W_MASK = 0x1,
|
||||
PVS_DST_WE_W_SHIFT = 23,
|
||||
PVS_DST_VE_SAT_MASK = 0x1,
|
||||
PVS_DST_VE_SAT_SHIFT = 24,
|
||||
PVS_DST_ME_SAT_MASK = 0x1,
|
||||
PVS_DST_ME_SAT_SHIFT = 25,
|
||||
PVS_DST_PRED_ENABLE_MASK = 0x1,
|
||||
PVS_DST_PRED_ENABLE_SHIFT = 26,
|
||||
PVS_DST_PRED_SENSE_MASK = 0x1,
|
||||
PVS_DST_PRED_SENSE_SHIFT = 27,
|
||||
PVS_DST_DUAL_MATH_OP_MASK = 0x3,
|
||||
PVS_DST_DUAL_MATH_OP_SHIFT = 27,
|
||||
PVS_DST_ADDR_SEL_MASK = 0x3,
|
||||
PVS_DST_ADDR_SEL_SHIFT = 29,
|
||||
PVS_DST_ADDR_MODE_0_MASK = 0x1,
|
||||
PVS_DST_ADDR_MODE_0_SHIFT = 31,
|
||||
};
|
||||
|
||||
/* PVS Source Operand Description */
|
||||
|
||||
enum {
|
||||
PVS_SRC_REG_TYPE_MASK = 0x3,
|
||||
PVS_SRC_REG_TYPE_SHIFT = 0,
|
||||
SPARE_0_MASK = 0x1,
|
||||
SPARE_0_SHIFT = 2,
|
||||
PVS_SRC_ABS_XYZW_MASK = 0x1,
|
||||
PVS_SRC_ABS_XYZW_SHIFT = 3,
|
||||
PVS_SRC_ADDR_MODE_0_MASK = 0x1,
|
||||
PVS_SRC_ADDR_MODE_0_SHIFT = 4,
|
||||
PVS_SRC_OFFSET_MASK = 0xff,
|
||||
PVS_SRC_OFFSET_SHIFT = 5,
|
||||
PVS_SRC_SWIZZLE_X_MASK = 0x7,
|
||||
PVS_SRC_SWIZZLE_X_SHIFT = 13,
|
||||
PVS_SRC_SWIZZLE_Y_MASK = 0x7,
|
||||
PVS_SRC_SWIZZLE_Y_SHIFT = 16,
|
||||
PVS_SRC_SWIZZLE_Z_MASK = 0x7,
|
||||
PVS_SRC_SWIZZLE_Z_SHIFT = 19,
|
||||
PVS_SRC_SWIZZLE_W_MASK = 0x7,
|
||||
PVS_SRC_SWIZZLE_W_SHIFT = 22,
|
||||
PVS_SRC_MODIFIER_X_MASK = 0x1,
|
||||
PVS_SRC_MODIFIER_X_SHIFT = 25,
|
||||
PVS_SRC_MODIFIER_Y_MASK = 0x1,
|
||||
PVS_SRC_MODIFIER_Y_SHIFT = 26,
|
||||
PVS_SRC_MODIFIER_Z_MASK = 0x1,
|
||||
PVS_SRC_MODIFIER_Z_SHIFT = 27,
|
||||
PVS_SRC_MODIFIER_W_MASK = 0x1,
|
||||
PVS_SRC_MODIFIER_W_SHIFT = 28,
|
||||
PVS_SRC_ADDR_SEL_MASK = 0x3,
|
||||
PVS_SRC_ADDR_SEL_SHIFT = 29,
|
||||
PVS_SRC_ADDR_MODE_1_MASK = 0x0,
|
||||
PVS_SRC_ADDR_MODE_1_SHIFT = 32,
|
||||
};
|
||||
|
||||
/*\}*/
|
||||
|
||||
/* BEGIN: Packet 3 commands */
|
||||
|
||||
|
|
@ -2613,3 +2687,5 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
|
|||
#endif /* _R300_REG_H */
|
||||
|
||||
/* *INDENT-ON* */
|
||||
|
||||
/* vim: set foldenable foldmarker=\\{,\\} foldmethod=marker : */
|
||||
|
|
|
|||
|
|
@ -1659,10 +1659,10 @@ static void r300SetupDefaultVertexProgram(r300ContextPtr rmesa)
|
|||
|
||||
for (i = VERT_ATTRIB_POS; i < VERT_ATTRIB_MAX; i++) {
|
||||
if (rmesa->state.sw_tcl_inputs[i] != -1) {
|
||||
prog->program.body.i[program_end + 0] = EASY_VSF_OP(MUL, o_reg++, ALL, RESULT);
|
||||
prog->program.body.i[program_end + 1] = VSF_REG(rmesa->state.sw_tcl_inputs[i]);
|
||||
prog->program.body.i[program_end + 2] = VSF_ATTR_UNITY(rmesa->state.sw_tcl_inputs[i]);
|
||||
prog->program.body.i[program_end + 3] = VSF_UNITY(rmesa->state.sw_tcl_inputs[i]);
|
||||
prog->program.body.i[program_end + 0] = PVS_OP_DST_OPERAND(VE_MULTIPLY, GL_FALSE, GL_FALSE, o_reg++, VSF_FLAG_ALL, PVS_DST_REG_OUT);
|
||||
prog->program.body.i[program_end + 1] = PVS_SRC_OPERAND(rmesa->state.sw_tcl_inputs[i], PVS_SRC_SELECT_X, PVS_SRC_SELECT_Y, PVS_SRC_SELECT_Z, PVS_SRC_SELECT_W, PVS_SRC_REG_INPUT, VSF_FLAG_NONE);
|
||||
prog->program.body.i[program_end + 2] = PVS_SRC_OPERAND(rmesa->state.sw_tcl_inputs[i], PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_REG_INPUT, VSF_FLAG_NONE);
|
||||
prog->program.body.i[program_end + 3] = PVS_SRC_OPERAND(rmesa->state.sw_tcl_inputs[i], PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_REG_INPUT, VSF_FLAG_NONE);
|
||||
program_end += 4;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -3,6 +3,25 @@
|
|||
|
||||
#include "r300_reg.h"
|
||||
|
||||
#define PVS_OP_DST_OPERAND(opcode, math_inst, macro_inst, reg_index, reg_writemask, reg_class) \
|
||||
(((opcode & PVS_DST_OPCODE_MASK) << PVS_DST_OPCODE_SHIFT) \
|
||||
| ((math_inst & PVS_DST_MATH_INST_MASK) << PVS_DST_MATH_INST_SHIFT) \
|
||||
| ((macro_inst & PVS_DST_MACRO_INST_MASK) << PVS_DST_MACRO_INST_SHIFT) \
|
||||
| ((reg_index & PVS_DST_OFFSET_MASK) << PVS_DST_OFFSET_SHIFT) \
|
||||
| ((reg_writemask & 0xf) << PVS_DST_WE_X_SHIFT) /* X Y Z W */ \
|
||||
| ((reg_class & PVS_DST_REG_TYPE_MASK) << PVS_DST_REG_TYPE_SHIFT))
|
||||
|
||||
#define PVS_SRC_OPERAND(in_reg_index, comp_x, comp_y, comp_z, comp_w, reg_class, negate) \
|
||||
(((in_reg_index & PVS_SRC_OFFSET_MASK) << PVS_SRC_OFFSET_SHIFT) \
|
||||
| ((comp_x & PVS_SRC_SWIZZLE_X_MASK) << PVS_SRC_SWIZZLE_X_SHIFT) \
|
||||
| ((comp_y & PVS_SRC_SWIZZLE_Y_MASK) << PVS_SRC_SWIZZLE_Y_SHIFT) \
|
||||
| ((comp_z & PVS_SRC_SWIZZLE_Z_MASK) << PVS_SRC_SWIZZLE_Z_SHIFT) \
|
||||
| ((comp_w & PVS_SRC_SWIZZLE_W_MASK) << PVS_SRC_SWIZZLE_W_SHIFT) \
|
||||
| ((negate & 0xf) << PVS_SRC_MODIFIER_X_SHIFT) /* X Y Z W */ \
|
||||
| ((reg_class & PVS_SRC_REG_TYPE_MASK) << PVS_SRC_REG_TYPE_SHIFT))
|
||||
|
||||
#if 1
|
||||
|
||||
#define VSF_FLAG_X 1
|
||||
#define VSF_FLAG_Y 2
|
||||
#define VSF_FLAG_Z 4
|
||||
|
|
@ -11,74 +30,6 @@
|
|||
#define VSF_FLAG_ALL 0xf
|
||||
#define VSF_FLAG_NONE 0
|
||||
|
||||
#define VSF_OUT_CLASS_TMP 0
|
||||
#define VSF_OUT_CLASS_ADDR 1
|
||||
#define VSF_OUT_CLASS_RESULT 2
|
||||
|
||||
/* first DWORD of an instruction */
|
||||
|
||||
/* possible operations:
|
||||
DOT, MUL, ADD, MAD, FRC, MAX, MIN, SGE, SLT, EXP, LOG, LIT, POW, RCP, RSQ, EX2,
|
||||
LG2, MAD_2 */
|
||||
|
||||
#define MAKE_VSF_OP(op, out_reg_index, out_reg_fields, class) \
|
||||
((op) \
|
||||
| ((out_reg_index) << R300_VPI_OUT_REG_INDEX_SHIFT) \
|
||||
| ((out_reg_fields) << 20) \
|
||||
| ( (class) << 8 ) )
|
||||
|
||||
#define EASY_VSF_OP(op, out_reg_index, out_reg_fields, class) \
|
||||
MAKE_VSF_OP(R300_VPI_OUT_OP_##op, out_reg_index, VSF_FLAG_##out_reg_fields, VSF_OUT_CLASS_##class) \
|
||||
|
||||
/* according to Nikolai, the subsequent 3 DWORDs are sources, use same define for each */
|
||||
|
||||
#define VSF_IN_CLASS_TMP 0
|
||||
#define VSF_IN_CLASS_ATTR 1
|
||||
#define VSF_IN_CLASS_PARAM 2
|
||||
#define VSF_IN_CLASS_NONE 9
|
||||
|
||||
#define VSF_IN_COMPONENT_X 0
|
||||
#define VSF_IN_COMPONENT_Y 1
|
||||
#define VSF_IN_COMPONENT_Z 2
|
||||
#define VSF_IN_COMPONENT_W 3
|
||||
#define VSF_IN_COMPONENT_ZERO 4
|
||||
#define VSF_IN_COMPONENT_ONE 5
|
||||
|
||||
#define MAKE_VSF_SOURCE(in_reg_index, comp_x, comp_y, comp_z, comp_w, class, negate) \
|
||||
( ((in_reg_index)<<R300_VPI_IN_REG_INDEX_SHIFT) \
|
||||
| ((comp_x)<<R300_VPI_IN_X_SHIFT) \
|
||||
| ((comp_y)<<R300_VPI_IN_Y_SHIFT) \
|
||||
| ((comp_z)<<R300_VPI_IN_Z_SHIFT) \
|
||||
| ((comp_w)<<R300_VPI_IN_W_SHIFT) \
|
||||
| ((negate)<<25) | ((class)))
|
||||
|
||||
#define EASY_VSF_SOURCE(in_reg_index, comp_x, comp_y, comp_z, comp_w, class, negate) \
|
||||
MAKE_VSF_SOURCE(in_reg_index, \
|
||||
VSF_IN_COMPONENT_##comp_x, \
|
||||
VSF_IN_COMPONENT_##comp_y, \
|
||||
VSF_IN_COMPONENT_##comp_z, \
|
||||
VSF_IN_COMPONENT_##comp_w, \
|
||||
VSF_IN_CLASS_##class, VSF_FLAG_##negate)
|
||||
|
||||
/* special sources: */
|
||||
|
||||
/* (1.0,1.0,1.0,1.0) vector (ATTR, plain ) */
|
||||
#define VSF_ATTR_UNITY(reg) EASY_VSF_SOURCE(reg, ONE, ONE, ONE, ONE, ATTR, NONE)
|
||||
#define VSF_UNITY(reg) EASY_VSF_SOURCE(reg, ONE, ONE, ONE, ONE, NONE, NONE)
|
||||
|
||||
/* contents of unmodified register */
|
||||
#define VSF_REG(reg) EASY_VSF_SOURCE(reg, X, Y, Z, W, ATTR, NONE)
|
||||
|
||||
/* contents of unmodified parameter */
|
||||
#define VSF_PARAM(reg) EASY_VSF_SOURCE(reg, X, Y, Z, W, PARAM, NONE)
|
||||
|
||||
/* contents of unmodified temporary register */
|
||||
#define VSF_TMP(reg) EASY_VSF_SOURCE(reg, X, Y, Z, W, TMP, NONE)
|
||||
|
||||
/* components of ATTR register */
|
||||
#define VSF_ATTR_X(reg) EASY_VSF_SOURCE(reg, X, X, X, X, ATTR, NONE)
|
||||
#define VSF_ATTR_Y(reg) EASY_VSF_SOURCE(reg, Y, Y, Y, Y, ATTR, NONE)
|
||||
#define VSF_ATTR_Z(reg) EASY_VSF_SOURCE(reg, Z, Z, Z, Z, ATTR, NONE)
|
||||
#define VSF_ATTR_W(reg) EASY_VSF_SOURCE(reg, W, W, W, W, ATTR, NONE)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue