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nvc0: remove an attempt at uploading all IMMD into a CB

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This has never been used because info->immd.bufSize is always 0
and anyways this is an experimental code which has never been
completed.

This gets rid of some unused code in the program validation process.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
This commit is contained in:
Samuel Pitoiset 2016-08-31 17:42:05 +02:00
parent b2f3d50ca7
commit 3df8615dcd
3 changed files with 0 additions and 40 deletions
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17
src/gallium/drivers/nouveau/nvc0/nvc0_program.c
View file

@ -604,8 +604,6 @@ nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset,
prog->code = info->bin.code;
prog->code_size = info->bin.codeSize;
prog->immd_data = info->immd.buf;
prog->immd_size = info->immd.bufSize;
prog->relocs = info->bin.relocData;
prog->fixups = info->bin.fixupData;
prog->num_gprs = MAX2(4, (info->bin.maxGPR + 1));
@ -692,13 +690,6 @@ nvc0_program_upload_code(struct nvc0_context *nvc0, struct nvc0_program *prog)
uint32_t lib_pos = screen->lib_code->start;
uint32_t code_pos;
/* c[] bindings need to be aligned to 0x100, but we could use relocations
* to save space. */
if (prog->immd_size) {
prog->immd_base = size;
size = align(size, 0x40);
size += prog->immd_size + 0xc0; /* add 0xc0 for align 0x40 -> 0x100 */
}
/* On Fermi, SP_START_ID must be aligned to 0x40.
* On Kepler, the first instruction must be aligned to 0x80 because
* latency information is expected only at certain positions.
@ -726,9 +717,6 @@ nvc0_program_upload_code(struct nvc0_context *nvc0, struct nvc0_program *prog)
IMMED_NVC0(nvc0->base.pushbuf, NVC0_3D(SERIALIZE), 0);
}
prog->code_base = prog->mem->start;
prog->immd_base = align(prog->mem->start + prog->immd_base, 0x100);
assert((prog->immd_size == 0) || (prog->immd_base + prog->immd_size <=
prog->mem->start + prog->mem->size));
if (!is_cp) {
if (screen->base.class_3d >= NVE4_3D_CLASS) {
@ -783,10 +771,6 @@ nvc0_program_upload_code(struct nvc0_context *nvc0, struct nvc0_program *prog)
NV_VRAM_DOMAIN(&screen->base), NVC0_SHADER_HEADER_SIZE, prog->hdr);
nvc0->base.push_data(&nvc0->base, screen->text, code_pos,
NV_VRAM_DOMAIN(&screen->base), prog->code_size, prog->code);
if (prog->immd_size)
nvc0->base.push_data(&nvc0->base,
screen->text, prog->immd_base, NV_VRAM_DOMAIN(&screen->base),
prog->immd_size, prog->immd_data);
BEGIN_NVC0(nvc0->base.pushbuf, NVC0_3D(MEM_BARRIER), 1);
PUSH_DATA (nvc0->base.pushbuf, 0x1011);
@ -830,7 +814,6 @@ nvc0_program_destroy(struct nvc0_context *nvc0, struct nvc0_program *prog)
if (prog->mem)
nouveau_heap_free(&prog->mem);
FREE(prog->code); /* may be 0 for hardcoded shaders */
FREE(prog->immd_data);
FREE(prog->relocs);
FREE(prog->fixups);
if (prog->type == PIPE_SHADER_COMPUTE && prog->cp.syms)

3
src/gallium/drivers/nouveau/nvc0/nvc0_program.h
View file

@ -26,11 +26,8 @@ struct nvc0_program {
uint8_t num_gprs;
uint32_t *code;
uint32_t *immd_data;
unsigned code_base;
unsigned code_size;
unsigned immd_base;
unsigned immd_size; /* size of immediate array data */
unsigned parm_size; /* size of non-bindable uniforms (c0[]) */
uint32_t hdr[20];

20
src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c
View file

@ -34,8 +34,6 @@ static inline void
nvc0_program_update_context_state(struct nvc0_context *nvc0,
struct nvc0_program *prog, int stage)
{
struct nouveau_pushbuf *push = nvc0->base.pushbuf;
if (prog && prog->need_tls) {
const uint32_t flags = NV_VRAM_DOMAIN(&nvc0->screen->base) | NOUVEAU_BO_RDWR;
if (!nvc0->state.tls_required)
@ -46,24 +44,6 @@ nvc0_program_update_context_state(struct nvc0_context *nvc0,
nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TLS);
nvc0->state.tls_required &= ~(1 << stage);
}
if (prog && prog->immd_size) {
BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
/* NOTE: may overlap code of a different shader */
PUSH_DATA (push, align(prog->immd_size, 0x100));
PUSH_DATAh(push, nvc0->screen->text->offset + prog->immd_base);
PUSH_DATA (push, nvc0->screen->text->offset + prog->immd_base);
BEGIN_NVC0(push, NVC0_3D(CB_BIND(stage)), 1);
PUSH_DATA (push, (14 << 4) | 1);
nvc0->state.c14_bound |= 1 << stage;
} else
if (nvc0->state.c14_bound & (1 << stage)) {
BEGIN_NVC0(push, NVC0_3D(CB_BIND(stage)), 1);
PUSH_DATA (push, (14 << 4) | 0);
nvc0->state.c14_bound &= ~(1 << stage);
}
}
static inline bool