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radeonsi: put si_pm4_state at the beginning of si_shader
instead of allocating it separately. This removes pointer indirections. Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12343>
This commit is contained in:
Marek Olšák
Marge Bot
parent
73c82570cb
commit
3df035d08c
6 changed files with 107 additions and 119 deletions
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@ -117,8 +117,8 @@ void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state)
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{
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struct radeon_cmdbuf *cs = &sctx->gfx_cs;
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if (state->shader) {
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radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, state->shader->bo,
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if (state->is_shader) {
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radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, ((struct si_shader*)state)->bo,
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RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
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}
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@ -139,7 +139,7 @@ void si_pm4_reset_emitted(struct si_context *sctx, bool first_cs)
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for (unsigned i = 0; i < SI_NUM_STATES; i++) {
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struct si_pm4_state *state = sctx->emitted.array[i];
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if (state && state->shader) {
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if (state && state->is_shader) {
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sctx->emitted.array[i] = NULL;
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sctx->dirty_states |= 1 << i;
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}
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@ -54,7 +54,7 @@ struct si_pm4_state {
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uint32_t pm4[SI_PM4_MAX_DW];
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/* For shader states only */
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struct si_shader *shader;
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bool is_shader;
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struct si_atom atom;
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};
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@ -138,6 +138,7 @@
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#include "util/u_inlines.h"
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#include "util/u_live_shader_cache.h"
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#include "util/u_queue.h"
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#include "si_pm4.h"
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#include <stdio.h>
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@ -772,6 +773,7 @@ union si_vgt_stages_key {
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};
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struct si_shader {
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struct si_pm4_state pm4; /* base class */
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struct si_compiler_ctx_state compiler_ctx_state;
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struct si_shader_selector *selector;
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@ -783,7 +785,6 @@ struct si_shader {
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struct si_shader_part *prolog2;
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struct si_shader_part *epilog;
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struct si_pm4_state *pm4;
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struct si_resource *bo;
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struct si_resource *scratch_bo;
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struct si_shader_key key;
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@ -183,13 +183,13 @@ union si_state {
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struct si_state_rasterizer *rasterizer;
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struct si_state_dsa *dsa;
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struct si_pm4_state *poly_offset;
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struct si_pm4_state *ls;
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struct si_pm4_state *hs;
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struct si_pm4_state *es;
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struct si_pm4_state *gs;
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struct si_shader *ls;
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struct si_shader *hs;
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struct si_shader *es;
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struct si_shader *gs;
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struct si_pm4_state *vgt_shader_config;
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struct si_pm4_state *vs;
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struct si_pm4_state *ps;
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struct si_shader *vs;
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struct si_shader *ps;
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} named;
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struct si_pm4_state *array[sizeof(struct si_state_named) / sizeof(struct si_pm4_state *)];
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};
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@ -127,7 +127,7 @@ static bool si_update_shaders(struct si_context *sctx)
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r = si_shader_select(ctx, &sctx->shader.tcs);
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if (r)
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return false;
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si_pm4_bind_state(sctx, hs, sctx->shader.tcs.current->pm4);
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si_pm4_bind_state(sctx, hs, sctx->shader.tcs.current);
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} else {
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if (!sctx->fixed_func_tcs_shader.cso) {
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sctx->fixed_func_tcs_shader.cso =
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@ -142,7 +142,7 @@ static bool si_update_shaders(struct si_context *sctx)
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r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader);
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if (r)
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return false;
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si_pm4_bind_state(sctx, hs, sctx->fixed_func_tcs_shader.current->pm4);
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si_pm4_bind_state(sctx, hs, sctx->fixed_func_tcs_shader.current);
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}
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if (!HAS_GS || GFX_VERSION <= GFX8) {
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@ -153,11 +153,11 @@ static bool si_update_shaders(struct si_context *sctx)
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if (HAS_GS) {
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/* TES as ES */
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assert(GFX_VERSION <= GFX8);
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si_pm4_bind_state(sctx, es, sctx->shader.tes.current->pm4);
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si_pm4_bind_state(sctx, es, sctx->shader.tes.current);
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} else if (NGG) {
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si_pm4_bind_state(sctx, gs, sctx->shader.tes.current->pm4);
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si_pm4_bind_state(sctx, gs, sctx->shader.tes.current);
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} else {
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si_pm4_bind_state(sctx, vs, sctx->shader.tes.current->pm4);
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si_pm4_bind_state(sctx, vs, sctx->shader.tes.current);
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}
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}
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} else {
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@ -174,9 +174,9 @@ static bool si_update_shaders(struct si_context *sctx)
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r = si_shader_select(ctx, &sctx->shader.gs);
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if (r)
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return false;
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si_pm4_bind_state(sctx, gs, sctx->shader.gs.current->pm4);
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si_pm4_bind_state(sctx, gs, sctx->shader.gs.current);
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if (!NGG) {
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si_pm4_bind_state(sctx, vs, sctx->shader.gs.cso->gs_copy_shader->pm4);
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si_pm4_bind_state(sctx, vs, sctx->shader.gs.cso->gs_copy_shader);
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if (!si_update_gs_ring_buffers(sctx))
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return false;
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@ -203,23 +203,23 @@ static bool si_update_shaders(struct si_context *sctx)
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if (!HAS_TESS && !HAS_GS) {
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if (NGG) {
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si_pm4_bind_state(sctx, gs, sctx->shader.vs.current->pm4);
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si_pm4_bind_state(sctx, gs, sctx->shader.vs.current);
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si_pm4_bind_state(sctx, vs, NULL);
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sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
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} else {
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si_pm4_bind_state(sctx, vs, sctx->shader.vs.current->pm4);
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si_pm4_bind_state(sctx, vs, sctx->shader.vs.current);
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}
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} else if (HAS_TESS) {
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si_pm4_bind_state(sctx, ls, sctx->shader.vs.current->pm4);
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si_pm4_bind_state(sctx, ls, sctx->shader.vs.current);
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} else {
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assert(HAS_GS);
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si_pm4_bind_state(sctx, es, sctx->shader.vs.current->pm4);
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si_pm4_bind_state(sctx, es, sctx->shader.vs.current);
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}
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}
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sctx->vs_uses_base_instance =
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sctx->shader.vs.current ? sctx->shader.vs.current->uses_base_instance :
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sctx->queued.named.hs ? sctx->queued.named.hs->shader->uses_base_instance :
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sctx->queued.named.hs ? sctx->queued.named.hs->uses_base_instance :
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sctx->shader.gs.current->uses_base_instance;
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union si_vgt_stages_key key;
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@ -244,7 +244,7 @@ static bool si_update_shaders(struct si_context *sctx)
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r = si_shader_select(ctx, &sctx->shader.ps);
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if (r)
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return false;
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si_pm4_bind_state(sctx, ps, sctx->shader.ps.current->pm4);
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si_pm4_bind_state(sctx, ps, sctx->shader.ps.current);
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if (si_pm4_state_changed(sctx, ps) ||
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(!NGG && si_pm4_state_changed(sctx, vs)) ||
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@ -310,7 +310,7 @@ static bool si_update_shaders(struct si_context *sctx)
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if (GFX_VERSION <= GFX8) /* LS */
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scratch_size = MAX2(scratch_size, sctx->shader.vs.current->config.scratch_bytes_per_wave);
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scratch_size = MAX2(scratch_size, sctx->queued.named.hs->shader->config.scratch_bytes_per_wave);
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scratch_size = MAX2(scratch_size, sctx->queued.named.hs->config.scratch_bytes_per_wave);
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if (HAS_GS) {
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if (GFX_VERSION <= GFX8) /* ES */
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@ -383,9 +383,9 @@ static unsigned si_conv_pipe_prim(unsigned mode)
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return prim_conv[mode];
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}
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static void si_prefetch_shader_async(struct si_context *sctx, struct si_pm4_state *state)
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static void si_prefetch_shader_async(struct si_context *sctx, struct si_shader *shader)
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{
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struct pipe_resource *bo = &state->shader->bo->b.b;
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struct pipe_resource *bo = &shader->bo->b.b;
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si_cp_dma_prefetch(sctx, bo, 0, bo->width0);
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}
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@ -373,7 +373,7 @@ bool si_shader_mem_ordered(struct si_shader *shader)
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}
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static void si_set_tesseval_regs(struct si_screen *sscreen, const struct si_shader_selector *tes,
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struct si_pm4_state *pm4)
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struct si_shader *shader)
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{
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const struct si_shader_info *info = &tes->info;
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unsigned tes_prim_mode = info->base.tess.primitive_mode;
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@ -430,8 +430,7 @@ static void si_set_tesseval_regs(struct si_screen *sscreen, const struct si_shad
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} else
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distribution_mode = V_028B6C_NO_DIST;
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assert(pm4->shader);
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pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) | S_028B6C_PARTITIONING(partitioning) |
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shader->vgt_tf_param = S_028B6C_TYPE(type) | S_028B6C_PARTITIONING(partitioning) |
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S_028B6C_TOPOLOGY(topology) |
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S_028B6C_DISTRIBUTION_MODE(distribution_mode);
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}
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@ -447,18 +446,16 @@ static void si_set_tesseval_regs(struct si_screen *sscreen, const struct si_shad
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* VS as ES | ES -> GS -> VS | 30
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* TES as VS | LS -> HS -> VS | 14 or 30
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* TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
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*
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* If "shader" is NULL, it's assumed it's not LS or GS copy shader.
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*/
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static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen, struct si_shader_selector *sel,
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struct si_shader *shader, struct si_pm4_state *pm4)
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struct si_shader *shader)
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{
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if (sscreen->info.family < CHIP_POLARIS10 || sscreen->info.chip_class >= GFX10)
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return;
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/* VS as VS, or VS as ES: */
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if ((sel->info.stage == MESA_SHADER_VERTEX &&
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(!shader || (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
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(!shader->key.as_ls && !shader->is_gs_copy_shader)) ||
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/* TES as VS, or TES as ES: */
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sel->info.stage == MESA_SHADER_TESS_EVAL) {
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unsigned vtx_reuse_depth = 30;
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@ -467,25 +464,15 @@ static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen, struct si_sh
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sel->info.base.tess.spacing == TESS_SPACING_FRACTIONAL_ODD)
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vtx_reuse_depth = 14;
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assert(pm4->shader);
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pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
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shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
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}
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}
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static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
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{
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if (shader->pm4)
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si_pm4_clear_state(shader->pm4);
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else
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shader->pm4 = CALLOC_STRUCT(si_pm4_state);
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if (shader->pm4) {
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shader->pm4->shader = shader;
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return shader->pm4;
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} else {
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fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
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return NULL;
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}
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si_pm4_clear_state(&shader->pm4);
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shader->pm4.is_shader = true;
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return &shader->pm4;
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}
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static unsigned si_get_num_vs_user_sgprs(struct si_shader *shader,
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@ -616,7 +603,7 @@ static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
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static void si_emit_shader_es(struct si_context *sctx)
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{
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struct si_shader *shader = sctx->queued.named.es->shader;
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struct si_shader *shader = sctx->queued.named.es;
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if (!shader)
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return;
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@ -677,9 +664,9 @@ static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
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S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
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if (shader->selector->info.stage == MESA_SHADER_TESS_EVAL)
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si_set_tesseval_regs(sscreen, shader->selector, pm4);
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si_set_tesseval_regs(sscreen, shader->selector, shader);
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polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
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polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader);
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}
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void gfx9_get_gs_info(struct si_shader_selector *es, struct si_shader_selector *gs,
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@ -777,7 +764,7 @@ void gfx9_get_gs_info(struct si_shader_selector *es, struct si_shader_selector *
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static void si_emit_shader_gs(struct si_context *sctx)
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{
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struct si_shader *shader = sctx->queued.named.gs->shader;
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struct si_shader *shader = sctx->queued.named.gs;
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if (!shader)
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return;
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@ -953,9 +940,9 @@ static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
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shader->ctx_reg.gs.vgt_esgs_ring_itemsize = shader->key.part.gs.es->esgs_itemsize / 4;
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if (es_stage == MESA_SHADER_TESS_EVAL)
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si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
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si_set_tesseval_regs(sscreen, shader->key.part.gs.es, shader);
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polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es, NULL, pm4);
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polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es, shader);
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} else {
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if (sscreen->info.chip_class >= GFX7) {
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si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
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@ -1046,7 +1033,7 @@ static void gfx10_emit_shader_ngg_tail(struct si_context *sctx, struct si_shader
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static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
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{
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struct si_shader *shader = sctx->queued.named.gs->shader;
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struct si_shader *shader = sctx->queued.named.gs;
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if (!shader)
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return;
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@ -1055,7 +1042,7 @@ static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
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static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
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{
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struct si_shader *shader = sctx->queued.named.gs->shader;
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struct si_shader *shader = sctx->queued.named.gs;
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if (!shader)
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return;
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@ -1069,7 +1056,7 @@ static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
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static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx)
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{
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struct si_shader *shader = sctx->queued.named.gs->shader;
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struct si_shader *shader = sctx->queued.named.gs;
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if (!shader)
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return;
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@ -1083,7 +1070,7 @@ static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx)
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static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx)
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{
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struct si_shader *shader = sctx->queued.named.gs->shader;
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struct si_shader *shader = sctx->queued.named.gs;
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if (!shader)
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return;
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@ -1267,7 +1254,7 @@ static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader
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}
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if (es_stage == MESA_SHADER_TESS_EVAL)
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si_set_tesseval_regs(sscreen, es_sel, pm4);
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si_set_tesseval_regs(sscreen, es_sel, shader);
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shader->ctx_reg.ngg.vgt_gs_onchip_cntl =
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S_028A44_ES_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
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@ -1356,7 +1343,7 @@ static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader
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static void si_emit_shader_vs(struct si_context *sctx)
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{
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struct si_shader *shader = sctx->queued.named.vs->shader;
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struct si_shader *shader = sctx->queued.named.vs;
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if (!shader)
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return;
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@ -1556,9 +1543,9 @@ static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
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S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
|
||||
|
||||
if (shader->selector->info.stage == MESA_SHADER_TESS_EVAL)
|
||||
si_set_tesseval_regs(sscreen, shader->selector, pm4);
|
||||
si_set_tesseval_regs(sscreen, shader->selector, shader);
|
||||
|
||||
polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
|
||||
polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader);
|
||||
}
|
||||
|
||||
static unsigned si_get_ps_num_interp(struct si_shader *ps)
|
||||
|
|
@ -1593,7 +1580,7 @@ static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
|
|||
|
||||
static void si_emit_shader_ps(struct si_context *sctx)
|
||||
{
|
||||
struct si_shader *shader = sctx->queued.named.ps->shader;
|
||||
struct si_shader *shader = sctx->queued.named.ps;
|
||||
if (!shader)
|
||||
return;
|
||||
|
||||
|
|
@ -3414,55 +3401,55 @@ static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
|
|||
|
||||
util_queue_fence_destroy(&shader->ready);
|
||||
|
||||
if (shader->pm4) {
|
||||
/* If destroyed shaders were not unbound, the next compiled
|
||||
* shader variant could get the same pointer address and so
|
||||
* binding it to the same shader stage would be considered
|
||||
* a no-op, causing random behavior.
|
||||
*/
|
||||
int state_index = -1;
|
||||
|
||||
switch (shader->selector->info.stage) {
|
||||
case MESA_SHADER_VERTEX:
|
||||
if (shader->key.as_ls) {
|
||||
assert(sctx->chip_class <= GFX8);
|
||||
si_pm4_free_state(sctx, shader->pm4, SI_STATE_IDX(ls));
|
||||
if (sctx->chip_class <= GFX8)
|
||||
state_index = SI_STATE_IDX(ls);
|
||||
} else if (shader->key.as_es) {
|
||||
assert(sctx->chip_class <= GFX8);
|
||||
si_pm4_free_state(sctx, shader->pm4, SI_STATE_IDX(es));
|
||||
if (sctx->chip_class <= GFX8)
|
||||
state_index = SI_STATE_IDX(es);
|
||||
} else if (shader->key.as_ngg) {
|
||||
si_pm4_free_state(sctx, shader->pm4, SI_STATE_IDX(gs));
|
||||
state_index = SI_STATE_IDX(gs);
|
||||
} else {
|
||||
si_pm4_free_state(sctx, shader->pm4, SI_STATE_IDX(vs));
|
||||
state_index = SI_STATE_IDX(vs);
|
||||
}
|
||||
break;
|
||||
case MESA_SHADER_TESS_CTRL:
|
||||
si_pm4_free_state(sctx, shader->pm4, SI_STATE_IDX(hs));
|
||||
state_index = SI_STATE_IDX(hs);
|
||||
break;
|
||||
case MESA_SHADER_TESS_EVAL:
|
||||
if (shader->key.as_es) {
|
||||
assert(sctx->chip_class <= GFX8);
|
||||
si_pm4_free_state(sctx, shader->pm4, SI_STATE_IDX(es));
|
||||
if (sctx->chip_class <= GFX8)
|
||||
state_index = SI_STATE_IDX(es);
|
||||
} else if (shader->key.as_ngg) {
|
||||
si_pm4_free_state(sctx, shader->pm4, SI_STATE_IDX(gs));
|
||||
state_index = SI_STATE_IDX(gs);
|
||||
} else {
|
||||
si_pm4_free_state(sctx, shader->pm4, SI_STATE_IDX(vs));
|
||||
state_index = SI_STATE_IDX(vs);
|
||||
}
|
||||
break;
|
||||
case MESA_SHADER_GEOMETRY:
|
||||
if (shader->is_gs_copy_shader)
|
||||
si_pm4_free_state(sctx, shader->pm4, SI_STATE_IDX(vs));
|
||||
state_index = SI_STATE_IDX(vs);
|
||||
else
|
||||
si_pm4_free_state(sctx, shader->pm4, SI_STATE_IDX(gs));
|
||||
state_index = SI_STATE_IDX(gs);
|
||||
break;
|
||||
case MESA_SHADER_FRAGMENT:
|
||||
si_pm4_free_state(sctx, shader->pm4, SI_STATE_IDX(ps));
|
||||
state_index = SI_STATE_IDX(ps);
|
||||
break;
|
||||
default:;
|
||||
}
|
||||
}
|
||||
|
||||
si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
|
||||
si_shader_destroy(shader);
|
||||
free(shader);
|
||||
si_pm4_free_state(sctx, &shader->pm4, state_index);
|
||||
}
|
||||
|
||||
static void si_destroy_shader_selector(struct pipe_context *ctx, void *cso)
|
||||
|
|
@ -3775,19 +3762,19 @@ static bool si_update_scratch_relocs(struct si_context *sctx)
|
|||
if (r < 0)
|
||||
return false;
|
||||
if (r == 1)
|
||||
si_pm4_bind_state(sctx, ps, sctx->shader.ps.current->pm4);
|
||||
si_pm4_bind_state(sctx, ps, sctx->shader.ps.current);
|
||||
|
||||
r = si_update_scratch_buffer(sctx, sctx->shader.gs.current);
|
||||
if (r < 0)
|
||||
return false;
|
||||
if (r == 1)
|
||||
si_pm4_bind_state(sctx, gs, sctx->shader.gs.current->pm4);
|
||||
si_pm4_bind_state(sctx, gs, sctx->shader.gs.current);
|
||||
|
||||
r = si_update_scratch_buffer(sctx, tcs);
|
||||
if (r < 0)
|
||||
return false;
|
||||
if (r == 1)
|
||||
si_pm4_bind_state(sctx, hs, tcs->pm4);
|
||||
si_pm4_bind_state(sctx, hs, tcs);
|
||||
|
||||
/* VS can be bound as LS, ES, or VS. */
|
||||
r = si_update_scratch_buffer(sctx, sctx->shader.vs.current);
|
||||
|
|
@ -3795,13 +3782,13 @@ static bool si_update_scratch_relocs(struct si_context *sctx)
|
|||
return false;
|
||||
if (r == 1) {
|
||||
if (sctx->shader.vs.current->key.as_ls)
|
||||
si_pm4_bind_state(sctx, ls, sctx->shader.vs.current->pm4);
|
||||
si_pm4_bind_state(sctx, ls, sctx->shader.vs.current);
|
||||
else if (sctx->shader.vs.current->key.as_es)
|
||||
si_pm4_bind_state(sctx, es, sctx->shader.vs.current->pm4);
|
||||
si_pm4_bind_state(sctx, es, sctx->shader.vs.current);
|
||||
else if (sctx->shader.vs.current->key.as_ngg)
|
||||
si_pm4_bind_state(sctx, gs, sctx->shader.vs.current->pm4);
|
||||
si_pm4_bind_state(sctx, gs, sctx->shader.vs.current);
|
||||
else
|
||||
si_pm4_bind_state(sctx, vs, sctx->shader.vs.current->pm4);
|
||||
si_pm4_bind_state(sctx, vs, sctx->shader.vs.current);
|
||||
}
|
||||
|
||||
/* TES can be bound as ES or VS. */
|
||||
|
|
@ -3810,11 +3797,11 @@ static bool si_update_scratch_relocs(struct si_context *sctx)
|
|||
return false;
|
||||
if (r == 1) {
|
||||
if (sctx->shader.tes.current->key.as_es)
|
||||
si_pm4_bind_state(sctx, es, sctx->shader.tes.current->pm4);
|
||||
si_pm4_bind_state(sctx, es, sctx->shader.tes.current);
|
||||
else if (sctx->shader.tes.current->key.as_ngg)
|
||||
si_pm4_bind_state(sctx, gs, sctx->shader.tes.current->pm4);
|
||||
si_pm4_bind_state(sctx, gs, sctx->shader.tes.current);
|
||||
else
|
||||
si_pm4_bind_state(sctx, vs, sctx->shader.tes.current->pm4);
|
||||
si_pm4_bind_state(sctx, vs, sctx->shader.tes.current);
|
||||
}
|
||||
|
||||
return true;
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue