From 3de108da663be66a2c60d500c6ba5cf2a4636eae Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Tue, 15 Jul 2025 12:07:47 +0200 Subject: [PATCH] radv/meta: update HiZ metadata after depth/stencil image clears Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/meta/radv_meta_clear.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/src/amd/vulkan/meta/radv_meta_clear.c b/src/amd/vulkan/meta/radv_meta_clear.c index 3963d58f643..c21a749d2a0 100644 --- a/src/amd/vulkan/meta/radv_meta_clear.c +++ b/src/amd/vulkan/meta/radv_meta_clear.c @@ -466,6 +466,7 @@ emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer, VkClearDepthStencilV bool can_fast_clear) { struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); + const struct radv_physical_device *pdev = radv_device_physical(device); const bool unrestricted = device->vk.enabled_extensions.EXT_depth_range_unrestricted; const struct radv_rendering_state *render = &cmd_buffer->state.render; uint32_t samples; @@ -538,6 +539,22 @@ emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer, VkClearDepthStencilV if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) { radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT, prev_reference); } + + if (iview && iview->image->hiz_valid_offset && radv_is_clear_rect_full(iview, clear_rect, view_mask)) { + assert(pdev->info.gfx_level == GFX12); + + const VkImageSubresourceRange range = { + .aspectMask = aspects, + .baseMipLevel = iview->vk.base_mip_level, + .levelCount = iview->vk.level_count, + .baseArrayLayer = iview->vk.base_array_layer, + .layerCount = iview->vk.layer_count, + }; + + radv_clear_hiz(cmd_buffer, iview->image, &range, radv_gfx12_get_hiz_initial_value()); + + radv_update_hiz_metadata(cmd_buffer, iview->image, &range, true); + } } static VkResult