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i965: Move VS load_input handling to nir_emit_vs_intrinsic().

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TCS/TES/GS and now FS all handle these in stage-specific functions.
CS don't have inputs, so VS was the only one left using this code.

Move it to the VS-specific function for clarity.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
This commit is contained in:
Kenneth Graunke 2016-07-19 19:00:19 -07:00
parent 1608209952
commit 3dba8516d6
1 changed files with 30 additions and 31 deletions
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61
src/mesa/drivers/dri/i965/brw_fs_nir.cpp
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@ -2358,6 +2358,36 @@ fs_visitor::nir_emit_vs_intrinsic(const fs_builder &bld,
break;
}
case nir_intrinsic_load_input: {
fs_reg src = fs_reg(ATTR, instr->const_index[0], dest.type);
unsigned num_components = instr->num_components;
enum brw_reg_type type = dest.type;
nir_const_value *const_offset = nir_src_as_const_value(instr->src[0]);
assert(const_offset && "Indirect input loads not allowed");
src = offset(src, bld, const_offset->u32[0]);
for (unsigned j = 0; j < num_components; j++) {
bld.MOV(offset(dest, bld, j), offset(src, bld, j));
}
if (type == BRW_REGISTER_TYPE_DF) {
/* Once the double vector is read, set again its original register
* type to continue with normal execution.
*/
src = retype(src, type);
dest = retype(dest, type);
}
if (type_sz(src.type) == 8) {
shuffle_32bit_load_result_to_64bit_data(bld,
dest,
retype(dest, BRW_REGISTER_TYPE_F),
instr->num_components);
}
break;
}
default:
nir_emit_intrinsic(bld, instr);
break;
@ -3968,37 +3998,6 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
break;
}
case nir_intrinsic_load_input: {
fs_reg src = fs_reg(ATTR, instr->const_index[0], dest.type);
unsigned num_components = instr->num_components;
enum brw_reg_type type = dest.type;
nir_const_value *const_offset = nir_src_as_const_value(instr->src[0]);
assert(const_offset && "Indirect input loads not allowed");
src = offset(src, bld, const_offset->u32[0]);
for (unsigned j = 0; j < num_components; j++) {
bld.MOV(offset(dest, bld, j), offset(src, bld, j));
}
if (type == BRW_REGISTER_TYPE_DF) {
/* Once the double vector is read, set again its original register
* type to continue with normal execution.
*/
src = retype(src, type);
dest = retype(dest, type);
}
if (type_sz(src.type) == 8) {
shuffle_32bit_load_result_to_64bit_data(bld,
dest,
retype(dest, BRW_REGISTER_TYPE_F),
instr->num_components);
}
break;
}
case nir_intrinsic_store_ssbo: {
assert(devinfo->gen >= 7);