From 3d5170c7057e2c99428f8ac9c19e9b71e64b82c1 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Fri, 30 Jan 2026 16:59:37 -0500 Subject: [PATCH] intel: add scheduling mode statistic This is for parity with what we do in the current GL shader-db path. Signed-off-by: Alyssa Rosenzweig Reviewed-by: Lionel Landwerlin Part-of: --- src/intel/compiler/brw/brw_generator.cpp | 1 + src/util/shader_stats.xml | 3 +++ 2 files changed, 4 insertions(+) diff --git a/src/intel/compiler/brw/brw_generator.cpp b/src/intel/compiler/brw/brw_generator.cpp index d7da994ac86..c3904cd7f7f 100644 --- a/src/intel/compiler/brw/brw_generator.cpp +++ b/src/intel/compiler/brw/brw_generator.cpp @@ -1457,6 +1457,7 @@ brw_generator::generate_code(const brw_shader &s, stats->non_ssa_regs_after_nir = shader_stats.non_ssa_registers_after_nir; stats->source_hash = prog_data->source_hash; stats->grf_registers = devinfo->ver >= 30 ? s.grf_used : 0; + stats->scheduler_mode = shader_stats.scheduler_mode; /* Report the max dispatch width only on the smallest SIMD variant. * diff --git a/src/util/shader_stats.xml b/src/util/shader_stats.xml index 7c764520a69..d7c8796749a 100644 --- a/src/util/shader_stats.xml +++ b/src/util/shader_stats.xml @@ -185,6 +185,9 @@ Hash generated from shader source. + + Scheduling mode selected for this binary. +