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freedreno: Add A605, A608, A610, A612 GPUs definition

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While we tested a610, a605/a608 are added by observing traces being same
to a610.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20991>
This commit is contained in:
Danylo Piliaiev 2023-01-30 18:28:52 +01:00 • committed by Marge Bot
parent 02ea3e4e10
commit 3d299bc7ef
1 changed files with 38 additions and 0 deletions
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38
src/freedreno/common/freedreno_devices.py
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@ -243,6 +243,14 @@ a6xx_gen1 = dict(
depth_bounds_require_depth_test_quirk = True,
)
# a605, a608, a610, 612
a6xx_gen1_low = {**a6xx_gen1, **dict(
has_gmem_fast_clear = False,
sysmem_per_ccu_cache_size = 8 * 1024,
gmem_ccu_color_cache_fraction = CCUColorCacheFraction.HALF.value,
vs_max_inputs_count = 16,
)}
# a640, a680:
a6xx_gen2 = dict(
fibers_per_sp = 128 * 4 * 16,
@ -304,6 +312,36 @@ a6xx_gen4 = dict(
has_per_view_viewport = True,
)
add_gpus([
GPUId(605), # TODO: Test it, based only on libwrapfake dumps
GPUId(608), # TODO: Test it, based only on libwrapfake dumps
GPUId(610),
GPUId(612), # TODO: Test it, based only on libwrapfake dumps
], A6xxGPUInfo(
CHIP.A6XX,
a6xx_gen1_low,
num_ccu = 1,
tile_align_w = 32,
tile_align_h = 16,
num_vsc_pipes = 16,
cs_shared_mem_size = 16 * 1024,
magic_regs = dict(
PC_POWER_CNTL = 0,
TPL1_DBG_ECO_CNTL = 0,
GRAS_DBG_ECO_CNTL = 0,
SP_CHICKEN_BITS = 0,
UCHE_CLIENT_PF = 0x00000004,
PC_MODE_CNTL = 0xf,
SP_DBG_ECO_CNTL = 0x0,
RB_DBG_ECO_CNTL = 0x04100000,
RB_DBG_ECO_CNTL_blit = 0x04100000,
HLSQ_DBG_ECO_CNTL = 0,
RB_UNKNOWN_8E01 = 0x00000001,
VPC_DBG_ECO_CNTL = 0x0,
UCHE_UNKNOWN_0E12 = 0x10000000,
),
))
add_gpus([
GPUId(615),
GPUId(616),