From 3d1efbce98bd76e337d2d07720afc49d5a41ca53 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Wed, 20 Aug 2025 17:50:15 +0200 Subject: [PATCH] radv: add a new dirty bit for the rast samples state Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 15 ++++++++++----- src/amd/vulkan/radv_cmd_buffer.h | 3 ++- 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index a97df9d95ff..2d2041dd6f1 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -3572,7 +3572,7 @@ radv_emit_patch_control_points(struct radv_cmd_buffer *cmd_buffer) } static void -radv_emit_rasterization_samples(struct radv_cmd_buffer *cmd_buffer) +radv_emit_rast_samples_state(struct radv_cmd_buffer *cmd_buffer) { struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const struct radv_physical_device *pdev = radv_device_physical(device); @@ -3632,6 +3632,8 @@ radv_emit_rasterization_samples(struct radv_cmd_buffer *cmd_buffer) radeon_set_context_reg(R_028A4C_PA_SC_MODE_CNTL_1, pa_sc_mode_cntl_1); radeon_end(); } + + cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_RAST_SAMPLES_STATE; } static void @@ -5402,10 +5404,6 @@ radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer, const ui if (states & RADV_DYNAMIC_TESS_DOMAIN_ORIGIN) radv_emit_tess_domain_origin(cmd_buffer); - if (states & (RADV_DYNAMIC_RASTERIZATION_SAMPLES | RADV_DYNAMIC_LINE_RASTERIZATION_MODE | RADV_DYNAMIC_POLYGON_MODE | - RADV_DYNAMIC_SAMPLE_LOCATIONS_ENABLE)) - radv_emit_rasterization_samples(cmd_buffer); - /* RADV_DYNAMIC_ATTACHMENT_FEEDBACK_LOOP_ENABLE is handled by radv_emit_db_shader_control. */ cmd_buffer->state.dirty_dynamic &= ~states; @@ -11460,6 +11458,10 @@ radv_validate_dynamic_states(struct radv_cmd_buffer *cmd_buffer, uint64_t dynami if (dynamic_states & RADV_DYNAMIC_FRAGMENT_SHADING_RATE) cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FSR_STATE; + + if (dynamic_states & (RADV_DYNAMIC_RASTERIZATION_SAMPLES | RADV_DYNAMIC_LINE_RASTERIZATION_MODE | + RADV_DYNAMIC_POLYGON_MODE | RADV_DYNAMIC_SAMPLE_LOCATIONS_ENABLE)) + cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RAST_SAMPLES_STATE; } static void @@ -11576,6 +11578,9 @@ radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer, const struct r if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FSR_STATE) radv_emit_fsr_state(cmd_buffer); + if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RAST_SAMPLES_STATE) + radv_emit_rast_samples_state(cmd_buffer); + if (gfx12_emit_alt_hiz_wa) radv_gfx12_emit_alt_hiz_wa(cmd_buffer); diff --git a/src/amd/vulkan/radv_cmd_buffer.h b/src/amd/vulkan/radv_cmd_buffer.h index 3a36d61fe63..b80f3bf8119 100644 --- a/src/amd/vulkan/radv_cmd_buffer.h +++ b/src/amd/vulkan/radv_cmd_buffer.h @@ -109,7 +109,8 @@ enum radv_cmd_dirty_bits { RADV_CMD_DIRTY_BINNING_STATE = 1ull << 23, RADV_CMD_DIRTY_NGGC_STATE = 1ull << 24, RADV_CMD_DIRTY_FSR_STATE = 1ull << 25, - RADV_CMD_DIRTY_ALL = (1ull << 26) - 1, + RADV_CMD_DIRTY_RAST_SAMPLES_STATE = 1ull << 26, + RADV_CMD_DIRTY_ALL = (1ull << 27) - 1, RADV_CMD_DIRTY_SHADER_QUERY = RADV_CMD_DIRTY_NGG_STATE | RADV_CMD_DIRTY_TASK_STATE, };