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radeonsi: fix DCC image stores with display DCC

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Fixes: 34a2c75310 - radeonsi: enable DCC stores on gfx10.3 APUs for better performance

Tested-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12809>
This commit is contained in:
Marek Olšák 2021-09-10 15:03:27 -04:00 • committed by Marge Bot
parent d4f7337d14
commit 3d1ca01e41
1 changed files with 13 additions and 3 deletions
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16
src/gallium/drivers/radeonsi/si_descriptors.c
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@ -360,9 +360,19 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture
state[6] |= S_00A018_META_PIPE_ALIGNED(meta.pipe_aligned) |
S_00A018_META_DATA_ADDRESS_LO(meta_va >> 8) |
/* DCC image stores require INDEPENDENT_128B_BLOCKS, which is not set
* with displayable DCC on Navi12-14 due to DCN limitations. */
S_00A018_WRITE_COMPRESS_ENABLE(tex->surface.u.gfx9.color.dcc.independent_128B_blocks &&
/* DCC image stores require the following settings:
* - INDEPENDENT_64B_BLOCKS = 0
* - INDEPENDENT_128B_BLOCKS = 1
* - MAX_COMPRESSED_BLOCK_SIZE = 128B
* - MAX_UNCOMPRESSED_BLOCK_SIZE = 256B (always used)
*
* The same limitations apply to SDMA compressed stores because
* SDMA uses the same DCC codec.
*/
S_00A018_WRITE_COMPRESS_ENABLE(!tex->surface.u.gfx9.color.dcc.independent_64B_blocks &&
tex->surface.u.gfx9.color.dcc.independent_128B_blocks &&
tex->surface.u.gfx9.color.dcc.max_compressed_block_size ==
V_028C78_MAX_BLOCK_SIZE_128B &&
access & SI_IMAGE_ACCESS_ALLOW_DCC_STORE);
}