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pan/lib: Adapt CRC calculation to align to 64x64 on v12+
The meta tile size changed on v12+ to 64x64 and the same apply to the checksum region size. Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34032>
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2 changed files with 20 additions and 12 deletions
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@ -26,6 +26,7 @@
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#include "util/log.h"
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#include "util/macros.h"
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#include "util/u_math.h"
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#include "pan_props.h"
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#include "pan_texture.h"
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/*
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@ -399,24 +400,29 @@ format_minimum_alignment(unsigned arch, enum pipe_format format, uint64_t mod)
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* Computes sizes for checksumming, which is 8 bytes per 16x16 tile.
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* Checksumming is believed to be a CRC variant (CRC64 based on the size?).
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* This feature is also known as "transaction elimination".
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* CRC values are prefetched by 32x32 regions so size needs to be aligned.
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* CRC values are prefetched by 32x32 (64x64 on v12+) regions so size needs to
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* be aligned.
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*/
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#define CHECKSUM_TILE_WIDTH 16
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#define CHECKSUM_TILE_HEIGHT 16
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#define CHECKSUM_REGION_SIZE 32
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#define CHECKSUM_X_TILE_PER_REGION (CHECKSUM_REGION_SIZE / CHECKSUM_TILE_WIDTH)
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#define CHECKSUM_Y_TILE_PER_REGION (CHECKSUM_REGION_SIZE / CHECKSUM_TILE_HEIGHT)
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#define CHECKSUM_BYTES_PER_TILE 8
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#define CHECKSUM_TILE_WIDTH 16
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#define CHECKSUM_TILE_HEIGHT 16
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#define CHECKSUM_BYTES_PER_TILE 8
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unsigned
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panfrost_compute_checksum_size(struct pan_image_slice_layout *slice,
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panfrost_compute_checksum_size(unsigned arch,
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struct pan_image_slice_layout *slice,
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unsigned width, unsigned height)
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{
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unsigned checksum_region_size = panfrost_meta_tile_size(arch);
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unsigned checksum_x_tile_per_region =
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(checksum_region_size / CHECKSUM_TILE_WIDTH);
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unsigned checksum_y_tile_per_region =
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(checksum_region_size / CHECKSUM_TILE_HEIGHT);
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unsigned tile_count_x =
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CHECKSUM_X_TILE_PER_REGION * DIV_ROUND_UP(width, CHECKSUM_REGION_SIZE);
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checksum_x_tile_per_region * DIV_ROUND_UP(width, checksum_region_size);
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unsigned tile_count_y =
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CHECKSUM_Y_TILE_PER_REGION * DIV_ROUND_UP(height, CHECKSUM_REGION_SIZE);
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checksum_y_tile_per_region * DIV_ROUND_UP(height, checksum_region_size);
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slice->crc.stride = tile_count_x * CHECKSUM_BYTES_PER_TILE;
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@ -651,7 +657,8 @@ pan_image_layout_init(unsigned arch, struct pan_image_layout *layout,
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/* Add a checksum region if necessary */
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if (layout->crc) {
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slice->crc.size = panfrost_compute_checksum_size(slice, width, height);
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slice->crc.size =
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panfrost_compute_checksum_size(arch, slice, width, height);
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slice->crc.offset = offset;
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offset += slice->crc.size;
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@ -252,7 +252,8 @@ pan_image_view_get_zs_plane(const struct pan_image_view *iview)
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return pan_image_view_get_plane(iview, 0);
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}
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unsigned panfrost_compute_checksum_size(struct pan_image_slice_layout *slice,
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unsigned panfrost_compute_checksum_size(unsigned arch,
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struct pan_image_slice_layout *slice,
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unsigned width, unsigned height);
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/* AFBC format mode. The ordering is intended to match the Valhall hardware enum
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