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radeonsi: don't use INDIRECT_BUFFER within IBs

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It's fragile. If I change the size or alignment, it hangs. Better safe than
sorry.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095>
This commit is contained in:
Marek Olšák 2020-05-18 23:14:03 -04:00
parent 8db739880a
commit 3cd96b5109
4 changed files with 0 additions and 35 deletions
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31
src/gallium/drivers/radeonsi/si_pm4.c
View file

@ -147,34 +147,3 @@ void si_pm4_reset_emitted(struct si_context *sctx)
memset(&sctx->emitted, 0, sizeof(sctx->emitted));
sctx->dirty_states |= u_bit_consecutive(0, SI_NUM_STATES);
}
void si_pm4_upload_indirect_buffer(struct si_context *sctx, struct si_pm4_state *state)
{
struct pipe_screen *screen = sctx->b.screen;
unsigned aligned_ndw = align(state->ndw, 8);
/* only supported on GFX7 and later */
if (sctx->chip_class < GFX7)
return;
assert(state->ndw);
assert(aligned_ndw <= SI_PM4_MAX_DW);
si_resource_reference(&state->indirect_buffer, NULL);
/* TODO: this hangs with 1024 or higher alignment on GFX9. */
state->indirect_buffer =
si_aligned_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, aligned_ndw * 4, 256);
if (!state->indirect_buffer)
return;
/* Pad the IB to 8 DWs to meet CP fetch alignment requirements. */
if (sctx->screen->info.gfx_ib_pad_with_type2) {
for (int i = state->ndw; i < aligned_ndw; i++)
state->pm4[i] = 0x80000000; /* type2 nop packet */
} else {
for (int i = state->ndw; i < aligned_ndw; i++)
state->pm4[i] = 0xffff1000; /* type3 nop packet */
}
pipe_buffer_write(&sctx->b, &state->indirect_buffer->b.b, 0, aligned_ndw * 4, state->pm4);
}

1
src/gallium/drivers/radeonsi/si_pm4.h
View file

@ -71,7 +71,6 @@ void si_pm4_cmd_end(struct si_pm4_state *state, bool predicate);
void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val);
void si_pm4_add_bo(struct si_pm4_state *state, struct si_resource *bo, enum radeon_bo_usage usage,
enum radeon_bo_priority priority);
void si_pm4_upload_indirect_buffer(struct si_context *sctx, struct si_pm4_state *state);
void si_pm4_clear_state(struct si_pm4_state *state);
void si_pm4_free_state(struct si_context *sctx, struct si_pm4_state *state, unsigned idx);

1
src/gallium/drivers/radeonsi/si_state.c
View file

@ -5415,6 +5415,5 @@ static void si_init_config(struct si_context *sctx)
si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
}
si_pm4_upload_indirect_buffer(sctx, pm4);
sctx->init_config = pm4;
}

2
src/gallium/drivers/radeonsi/si_state_shaders.c
View file

@ -3396,7 +3396,6 @@ static bool si_update_gs_ring_buffers(struct si_context *sctx)
if (!sctx->init_config_has_vgt_flush) {
si_init_config_add_vgt_flush(sctx);
si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
}
/* Flush the context to re-emit both init_config states. */
@ -3663,7 +3662,6 @@ static void si_init_tess_factor_ring(struct si_context *sctx)
/* Flush the context to re-emit the init_config state.
* This is done only once in a lifetime of a context.
*/
si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
sctx->initial_gfx_cs_size = 0; /* force flush */
si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
}