From 3cc53c047aef7d823446d86b575b41f7ebaad2a3 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Fri, 11 Feb 2022 16:44:39 +0100 Subject: [PATCH] radv: allow to force per-vertex VRS in the tessellation stage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It's more useful than I thought. Signed-off-by: Samuel Pitoiset Reviewed-by: Timur Kristóf Reviewed-by: Bas Nieuwenhuizen Part-of: --- src/amd/vulkan/radv_pipeline.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 153e5897b40..ea22e9c7250 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -3664,8 +3664,8 @@ radv_consider_force_vrs(const struct radv_pipeline *pipeline, bool noop_fs, nir_ if (!device->force_vrs_enabled) return false; - /* Only VS and GS are supported for now. */ if (pipeline->graphics.last_vgt_api_stage != MESA_SHADER_VERTEX && + pipeline->graphics.last_vgt_api_stage != MESA_SHADER_TESS_EVAL && pipeline->graphics.last_vgt_api_stage != MESA_SHADER_GEOMETRY) return false;