mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
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r600/sfn: Handle slot differences between pre-EG and EG
Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Reviewed-by: Filip Gawin <filip@gawin.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17822>
This commit is contained in:
Gert Wollny
Marge Bot
parent
dac627f6e0
commit
3c7368de56
6 changed files with 245 additions and 217 deletions
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@ -29,210 +29,210 @@
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namespace r600 {
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const std::map<EAluOp, AluOp> alu_ops = {
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{op0_nop ,AluOp(0, 0, AluOp::a,"NOP")},
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{op0_group_barrier ,AluOp(0, 0, AluOp::a,"GROUP_BARRIER")},
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{op0_group_seq_begin ,AluOp(0, 0, AluOp::a,"GROUP_SEQ_BEGIN")},
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{op0_group_seq_end ,AluOp(0, 0, AluOp::a,"GROUP_SEQ_END")},
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{op0_pred_set_clr ,AluOp(0, 1, AluOp::a,"PRED_SET_CLR")},
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{op0_store_flags ,AluOp(0, 0, AluOp::v,"STORE_FLAGS")},
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{op0_lds_1a ,AluOp(0, 0, AluOp::v,"LDS_1A")},
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{op0_lds_1a1d ,AluOp(0, 0, AluOp::v,"LDS_1A1D")},
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{op0_lds_2a ,AluOp(0, 0, AluOp::v,"LDS_2A")},
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{op0_nop ,AluOp(0, 0, AluOp::a, AluOp::a,"NOP")},
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{op0_group_barrier ,AluOp(0, 0, AluOp::a, AluOp::a,"GROUP_BARRIER")},
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{op0_group_seq_begin ,AluOp(0, 0, AluOp::a, AluOp::a,"GROUP_SEQ_BEGIN")},
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{op0_group_seq_end ,AluOp(0, 0, AluOp::a, AluOp::a,"GROUP_SEQ_END")},
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{op0_pred_set_clr ,AluOp(0, 1, AluOp::a, AluOp::a,"PRED_SET_CLR")},
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{op0_store_flags ,AluOp(0, 0, AluOp::v, AluOp::v,"STORE_FLAGS")},
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{op0_lds_1a ,AluOp(0, 0, AluOp::v, AluOp::v,"LDS_1A")},
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{op0_lds_1a1d ,AluOp(0, 0, AluOp::v, AluOp::v,"LDS_1A1D")},
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{op0_lds_2a ,AluOp(0, 0, AluOp::v, AluOp::v,"LDS_2A")},
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{op1_bcnt_int ,AluOp(1, 0, AluOp::v,"BCNT_INT")},
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{op1_bcnt_accum_prev_int ,AluOp(1, 0, AluOp::v,"BCNT_ACCUM_PREV_INT")},
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{op1_bfrev_int ,AluOp(1, 0, AluOp::a,"BFREV_INT")},
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{op1_ceil ,AluOp(1, 1, AluOp::a,"CEIL")},
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{op1_cos ,AluOp(1, 1, AluOp::t,"COS")},
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{op1_exp_ieee ,AluOp(1, 1, AluOp::t,"EXP_IEEE")},
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{op1_floor ,AluOp(1, 1, AluOp::a,"FLOOR")},
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{op1_flt_to_int ,AluOp(1, 0, AluOp::v,"FLT_TO_INT")},
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{op1_flt_to_uint ,AluOp(1, 1, AluOp::t,"FLT_TO_UINT")},
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{op1_flt_to_int_rpi ,AluOp(1, 1, AluOp::v,"FLT_TO_INT_RPI")},
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{op1_flt_to_int_floor ,AluOp(1, 1, AluOp::v,"FLT_TO_INT_FLOOR")},
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{op1_flt16_to_flt32 ,AluOp(1, 1, AluOp::v,"FLT16_TO_FLT32")},
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{op1_flt32_to_flt16 ,AluOp(1, 1, AluOp::v,"FLT32_TO_FLT16")},
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{op1_flt32_to_flt64 ,AluOp(1, 1, AluOp::v,"FLT32_TO_FLT64")},
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{op1_flt64_to_flt32 ,AluOp(1, 1, AluOp::a,"FLT64_TO_FLT32")},
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{op1_fract ,AluOp(1, 1, AluOp::a,"FRACT")},
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{op1_fract_64 ,AluOp(1, 1, AluOp::v,"FRACT_64")},
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{op1_frexp_64 ,AluOp(1, 1, AluOp::v,"FREXP_64")},
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{op1_int_to_flt ,AluOp(1, 0, AluOp::t,"INT_TO_FLT")},
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{op1_ldexp_64 ,AluOp(1, 1, AluOp::v,"LDEXP_64")},
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{op1_interp_load_p0 ,AluOp(1, 1, AluOp::v,"INTERP_LOAD_P0")},
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{op1_interp_load_p10 ,AluOp(1, 1, AluOp::v,"INTERP_LOAD_P10")},
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{op1_interp_load_p20 ,AluOp(1, 1, AluOp::v,"INTERP_LOAD_P20")},
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{op1_load_store_flags ,AluOp(1, 0, AluOp::v,"LOAD_STORE_FLAGS")},
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{op1_log_clamped ,AluOp(1, 1, AluOp::t,"LOG_CLAMPED")},
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{op1_log_ieee ,AluOp(1, 1, AluOp::t,"LOG_IEEE")},
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{op1_max4 ,AluOp(1, 1, AluOp::v,"MAX4")},
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{op1_mbcnt_32hi_int ,AluOp(1, 0, AluOp::v,"MBCNT_32HI_INT")},
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{op1_mbcnt_32lo_accum_prev_int ,AluOp(1, 0, AluOp::v,"MBCNT_32LO_ACCUM_PREV_INT")},
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{op1_mov ,AluOp(1, 0, AluOp::a,"MOV")},
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{op1_mova_int ,AluOp(1, 0, AluOp::v,"MOVA_INT")},
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{op1_not_int ,AluOp(1, 0, AluOp::a,"NOT_INT")},
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{op1_offset_to_flt ,AluOp(1, 0, AluOp::v,"OFFSET_TO_FLT")},
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{op1_pred_set_inv ,AluOp(1, 1, AluOp::a,"PRED_SET_INV")},
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{op1_pred_set_restore ,AluOp(1, 1, AluOp::a,"PRED_SET_RESTORE")},
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{op1_set_cf_idx0 ,AluOp(1, 0, AluOp::a,"SET_CF_IDX0")}, /* Reads from AR register? */
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{op1_set_cf_idx1 ,AluOp(1, 0, AluOp::a,"SET_CF_IDX1")}, /* Reads from AR register? */
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{op1_recip_clamped ,AluOp(1, 1, AluOp::t,"RECIP_CLAMPED")},
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{op1_recip_ff ,AluOp(1, 1, AluOp::t,"RECIP_FF")},
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{op1_recip_ieee ,AluOp(1, 1, AluOp::t,"RECIP_IEEE")},
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{op1_recipsqrt_clamped ,AluOp(1, 1, AluOp::t,"RECIPSQRT_CLAMPED")},
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{op1_recipsqrt_ff ,AluOp(1, 1, AluOp::t,"RECIPSQRT_FF")},
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{op1_recipsqrt_ieee1 ,AluOp(1, 1, AluOp::t,"RECIPSQRT_IEEE")},
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{op1_recip_int ,AluOp(1, 0, AluOp::t,"RECIP_INT")},
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{op1_recip_uint ,AluOp(1, 0, AluOp::t,"RECIP_UINT")},
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{op1_recip_64 ,AluOp(2, 1, AluOp::t,"RECIP_64")},
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{op1_recip_clamped_64 ,AluOp(2, 1, AluOp::t,"RECIP_CLAMPED_64")},
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{op1_recipsqrt_64 ,AluOp(2, 1, AluOp::t,"RECIPSQRT_64")},
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{op1_recipsqrt_clamped_64,AluOp(2, 1, AluOp::t,"RECIPSQRT_CLAMPED_64")},
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{op1_rndne ,AluOp(1, 1, AluOp::a,"RNDNE")},
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{op1_sqrt_ieee ,AluOp(1, 1, AluOp::t,"SQRT_IEEE")},
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{op1_sin ,AluOp(1, 1, AluOp::t,"SIN")},
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{op1_trunc ,AluOp(1, 1, AluOp::a,"TRUNC")},
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{op1_sqrt_64 ,AluOp(2, 1, AluOp::t,"SQRT_64")},
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{op1_ubyte0_flt ,AluOp(1, 1, AluOp::v,"UBYTE0_FLT")},
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{op1_ubyte1_flt ,AluOp(1, 1, AluOp::v,"UBYTE1_FLT")},
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{op1_ubyte2_flt ,AluOp(1, 1, AluOp::v,"UBYTE2_FLT")},
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{op1_ubyte3_flt ,AluOp(1, 1, AluOp::v,"UBYTE3_FLT")},
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{op1_uint_to_flt ,AluOp(1, 0, AluOp::t,"UINT_TO_FLT")},
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{op1_ffbh_uint ,AluOp(1, 0, AluOp::v,"FFBH_UINT")},
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{op1_ffbl_int ,AluOp(1, 0, AluOp::v,"FFBL_INT")},
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{op1_ffbh_int ,AluOp(1, 0, AluOp::v,"FFBH_INT")},
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{op1_flt_to_uint4 ,AluOp(1, 1, AluOp::v,"FLT_TO_UINT4")},
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{op1v_flt32_to_flt64 ,AluOp(1, 1, AluOp::a,"FLT32_TO_FLT64")},
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{op1v_flt64_to_flt32 ,AluOp(1, 1, AluOp::v,"FLT64_TO_FLT32")},
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{op1_bcnt_int ,AluOp(1, 0, AluOp::v, AluOp::v,"BCNT_INT")},
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{op1_bcnt_accum_prev_int ,AluOp(1, 0, AluOp::v, AluOp::v,"BCNT_ACCUM_PREV_INT")},
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{op1_bfrev_int ,AluOp(1, 0, AluOp::a, AluOp::a,"BFREV_INT")},
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{op1_ceil ,AluOp(1, 1, AluOp::a, AluOp::a,"CEIL")},
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{op1_cos ,AluOp(1, 1, AluOp::t, AluOp::t,"COS")},
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{op1_exp_ieee ,AluOp(1, 1, AluOp::t, AluOp::t,"EXP_IEEE")},
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{op1_floor ,AluOp(1, 1, AluOp::a, AluOp::a,"FLOOR")},
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{op1_flt_to_int ,AluOp(1, 0, AluOp::t, AluOp::v,"FLT_TO_INT")},
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{op1_flt_to_uint ,AluOp(1, 1, AluOp::t, AluOp::t,"FLT_TO_UINT")},
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{op1_flt_to_int_rpi ,AluOp(1, 1, AluOp::v, AluOp::v,"FLT_TO_INT_RPI")},
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{op1_flt_to_int_floor ,AluOp(1, 1, AluOp::v, AluOp::v,"FLT_TO_INT_FLOOR")},
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{op1_flt16_to_flt32 ,AluOp(1, 1, AluOp::v, AluOp::v,"FLT16_TO_FLT32")},
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{op1_flt32_to_flt16 ,AluOp(1, 1, AluOp::v, AluOp::v,"FLT32_TO_FLT16")},
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{op1_flt32_to_flt64 ,AluOp(1, 1, AluOp::v, AluOp::v,"FLT32_TO_FLT64")},
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{op1_flt64_to_flt32 ,AluOp(1, 1, AluOp::a, AluOp::a,"FLT64_TO_FLT32")},
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{op1_fract ,AluOp(1, 1, AluOp::a, AluOp::a,"FRACT")},
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{op1_fract_64 ,AluOp(1, 1, AluOp::v, AluOp::v,"FRACT_64")},
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{op1_frexp_64 ,AluOp(1, 1, AluOp::v, AluOp::v,"FREXP_64")},
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{op1_int_to_flt ,AluOp(1, 0, AluOp::t, AluOp::t,"INT_TO_FLT")},
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{op1_ldexp_64 ,AluOp(1, 1, AluOp::v, AluOp::v,"LDEXP_64")},
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{op1_interp_load_p0 ,AluOp(1, 1, AluOp::v, AluOp::v,"INTERP_LOAD_P0")},
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{op1_interp_load_p10 ,AluOp(1, 1, AluOp::v, AluOp::v,"INTERP_LOAD_P10")},
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{op1_interp_load_p20 ,AluOp(1, 1, AluOp::v, AluOp::v,"INTERP_LOAD_P20")},
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{op1_load_store_flags ,AluOp(1, 0, AluOp::v, AluOp::v,"LOAD_STORE_FLAGS")},
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{op1_log_clamped ,AluOp(1, 1, AluOp::t, AluOp::t,"LOG_CLAMPED")},
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{op1_log_ieee ,AluOp(1, 1, AluOp::t, AluOp::t,"LOG_IEEE")},
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{op1_max4 ,AluOp(1, 1, AluOp::v, AluOp::v,"MAX4")},
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{op1_mbcnt_32hi_int ,AluOp(1, 0, AluOp::v, AluOp::v,"MBCNT_32HI_INT")},
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{op1_mbcnt_32lo_accum_prev_int ,AluOp(1, 0, AluOp::v, AluOp::v,"MBCNT_32LO_ACCUM_PREV_INT")},
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{op1_mov ,AluOp(1, 0, AluOp::a, AluOp::a,"MOV")},
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{op1_mova_int ,AluOp(1, 0, AluOp::v, AluOp::v,"MOVA_INT")},
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{op1_not_int ,AluOp(1, 0, AluOp::a, AluOp::a,"NOT_INT")},
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{op1_offset_to_flt ,AluOp(1, 0, AluOp::v, AluOp::v,"OFFSET_TO_FLT")},
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{op1_pred_set_inv ,AluOp(1, 1, AluOp::a, AluOp::a,"PRED_SET_INV")},
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{op1_pred_set_restore ,AluOp(1, 1, AluOp::a, AluOp::a,"PRED_SET_RESTORE")},
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{op1_set_cf_idx0 ,AluOp(1, 0, AluOp::a, AluOp::a,"SET_CF_IDX0")}, /* Reads from AR register? */
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{op1_set_cf_idx1 ,AluOp(1, 0, AluOp::a, AluOp::a,"SET_CF_IDX1")}, /* Reads from AR register? */
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{op1_recip_clamped ,AluOp(1, 1, AluOp::t, AluOp::t,"RECIP_CLAMPED")},
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{op1_recip_ff ,AluOp(1, 1, AluOp::t, AluOp::t,"RECIP_FF")},
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{op1_recip_ieee ,AluOp(1, 1, AluOp::t, AluOp::t,"RECIP_IEEE")},
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{op1_recipsqrt_clamped ,AluOp(1, 1, AluOp::t, AluOp::t,"RECIPSQRT_CLAMPED")},
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{op1_recipsqrt_ff ,AluOp(1, 1, AluOp::t, AluOp::t,"RECIPSQRT_FF")},
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{op1_recipsqrt_ieee1 ,AluOp(1, 1, AluOp::t, AluOp::t,"RECIPSQRT_IEEE")},
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{op1_recip_int ,AluOp(1, 0, AluOp::t, AluOp::t,"RECIP_INT")},
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{op1_recip_uint ,AluOp(1, 0, AluOp::t, AluOp::t,"RECIP_UINT")},
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{op1_recip_64 ,AluOp(2, 1, AluOp::t, AluOp::t,"RECIP_64")},
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{op1_recip_clamped_64 ,AluOp(2, 1, AluOp::t, AluOp::t,"RECIP_CLAMPED_64")},
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{op1_recipsqrt_64 ,AluOp(2, 1, AluOp::t, AluOp::t,"RECIPSQRT_64")},
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{op1_recipsqrt_clamped_64,AluOp(2, 1, AluOp::t, AluOp::t,"RECIPSQRT_CLAMPED_64")},
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{op1_rndne ,AluOp(1, 1, AluOp::a, AluOp::a,"RNDNE")},
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{op1_sqrt_ieee ,AluOp(1, 1, AluOp::t, AluOp::t,"SQRT_IEEE")},
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{op1_sin ,AluOp(1, 1, AluOp::t, AluOp::t,"SIN")},
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{op1_trunc ,AluOp(1, 1, AluOp::a, AluOp::a,"TRUNC")},
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{op1_sqrt_64 ,AluOp(2, 1, AluOp::t, AluOp::t,"SQRT_64")},
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{op1_ubyte0_flt ,AluOp(1, 1, AluOp::v, AluOp::v,"UBYTE0_FLT")},
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{op1_ubyte1_flt ,AluOp(1, 1, AluOp::v, AluOp::v,"UBYTE1_FLT")},
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{op1_ubyte2_flt ,AluOp(1, 1, AluOp::v, AluOp::v,"UBYTE2_FLT")},
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{op1_ubyte3_flt ,AluOp(1, 1, AluOp::v, AluOp::v,"UBYTE3_FLT")},
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{op1_uint_to_flt ,AluOp(1, 0, AluOp::t, AluOp::t,"UINT_TO_FLT")},
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{op1_ffbh_uint ,AluOp(1, 0, AluOp::v, AluOp::v,"FFBH_UINT")},
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{op1_ffbl_int ,AluOp(1, 0, AluOp::v, AluOp::v,"FFBL_INT")},
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{op1_ffbh_int ,AluOp(1, 0, AluOp::v, AluOp::v,"FFBH_INT")},
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{op1_flt_to_uint4 ,AluOp(1, 1, AluOp::v, AluOp::v,"FLT_TO_UINT4")},
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{op1v_flt32_to_flt64 ,AluOp(1, 1, AluOp::a, AluOp::a,"FLT32_TO_FLT64")},
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{op1v_flt64_to_flt32 ,AluOp(1, 1, AluOp::v, AluOp::v,"FLT64_TO_FLT32")},
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{op2_add ,AluOp(2, 1, AluOp::a,"ADD")},
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{op2_bfm_int ,AluOp(2, 0, AluOp::v,"BFM_INT")},
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{op2_mul ,AluOp(2, 1, AluOp::a,"MUL")},
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{op2_mul_ieee ,AluOp(2, 1, AluOp::a,"MUL_IEEE")},
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{op2_max ,AluOp(2, 1, AluOp::a,"MAX")},
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{op2_min ,AluOp(2, 1, AluOp::a,"MIN")},
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{op2_max_dx10 ,AluOp(2, 1, AluOp::a,"MAX_DX10")},
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{op2_min_dx10 ,AluOp(2, 1, AluOp::a,"MIN_DX10")},
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{op2_sete ,AluOp(2, 1, AluOp::a,"SETE")},
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{op2_setgt ,AluOp(2, 1, AluOp::a,"SETGT")},
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{op2_setge ,AluOp(2, 1, AluOp::a,"SETGE")},
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{op2_setne ,AluOp(2, 1, AluOp::a,"SETNE")},
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{op2_sete_dx10 ,AluOp(2, 1, AluOp::a,"SETE_DX10")},
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{op2_setgt_dx10 ,AluOp(2, 1, AluOp::a,"SETGT_DX10")},
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{op2_setge_dx10 ,AluOp(2, 1, AluOp::a,"SETGE_DX10")},
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{op2_setne_dx10 ,AluOp(2, 1, AluOp::a,"SETNE_DX10")},
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{op2_ashr_int ,AluOp(2, 0, AluOp::a,"ASHR_INT")},
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{op2_lshr_int ,AluOp(2, 0, AluOp::a,"LSHR_INT")},
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{op2_lshl_int ,AluOp(2, 0, AluOp::a,"LSHL_INT")},
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{op2_mul_64 ,AluOp(2, 1, AluOp::a,"MUL_64")},
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{op2_pred_setgt_uint ,AluOp(2, 0, AluOp::a,"PRED_SETGT_UINT")},
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{op2_pred_setge_uint ,AluOp(2, 0, AluOp::a,"PRED_SETGE_UINT")},
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{op2_pred_sete ,AluOp(2, 1, AluOp::a,"PRED_SETE")},
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{op2_pred_setgt ,AluOp(2, 1, AluOp::a,"PRED_SETGT")},
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{op2_pred_setge ,AluOp(2, 1, AluOp::a,"PRED_SETGE")},
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{op2_pred_setne ,AluOp(2, 1, AluOp::a,"PRED_SETNE")},
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{op2_pred_set_pop ,AluOp(2, 1, AluOp::a,"PRED_SET_POP")},
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{op2_pred_sete_push ,AluOp(2, 1, AluOp::a,"PRED_SETE_PUSH")},
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{op2_pred_setgt_push ,AluOp(2, 1, AluOp::a,"PRED_SETGT_PUSH")},
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{op2_pred_setge_push ,AluOp(2, 1, AluOp::a,"PRED_SETGE_PUSH")},
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{op2_pred_setne_push ,AluOp(2, 1, AluOp::a,"PRED_SETNE_PUSH")},
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{op2_kille ,AluOp(2, 1, AluOp::a,"KILLE")},
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{op2_killgt ,AluOp(2, 1, AluOp::a,"KILLGT")},
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{op2_killge ,AluOp(2, 1, AluOp::a,"KILLGE")},
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{op2_killne ,AluOp(2, 1, AluOp::a,"KILLNE")},
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{op2_and_int ,AluOp(2, 0, AluOp::a,"AND_INT")},
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{op2_or_int ,AluOp(2, 0, AluOp::a,"OR_INT")},
|
||||
{op2_xor_int ,AluOp(2, 0, AluOp::a,"XOR_INT")},
|
||||
{op2_add_int ,AluOp(2, 0, AluOp::a,"ADD_INT")},
|
||||
{op2_sub_int ,AluOp(2, 0, AluOp::a,"SUB_INT")},
|
||||
{op2_max_int ,AluOp(2, 0, AluOp::a,"MAX_INT")},
|
||||
{op2_min_int ,AluOp(2, 0, AluOp::a,"MIN_INT")},
|
||||
{op2_max_uint ,AluOp(2, 0, AluOp::a,"MAX_UINT")},
|
||||
{op2_min_uint ,AluOp(2, 0, AluOp::a,"MIN_UINT")},
|
||||
{op2_sete_int ,AluOp(2, 0, AluOp::a,"SETE_INT")},
|
||||
{op2_setgt_int ,AluOp(2, 0, AluOp::a,"SETGT_INT")},
|
||||
{op2_setge_int ,AluOp(2, 0, AluOp::a,"SETGE_INT")},
|
||||
{op2_setne_int ,AluOp(2, 0, AluOp::a,"SETNE_INT")},
|
||||
{op2_setgt_uint ,AluOp(2, 0, AluOp::a,"SETGT_UINT")},
|
||||
{op2_setge_uint ,AluOp(2, 0, AluOp::a,"SETGE_UINT")},
|
||||
{op2_killgt_uint ,AluOp(2, 0, AluOp::a,"KILLGT_UINT")},
|
||||
{op2_killge_uint ,AluOp(2, 0, AluOp::a,"KILLGE_UINT")},
|
||||
{op2_prede_int ,AluOp(2, 0, AluOp::a,"PREDE_INT")},
|
||||
{op2_pred_setgt_int ,AluOp(2, 0, AluOp::a,"PRED_SETGT_INT")},
|
||||
{op2_pred_setge_int ,AluOp(2, 0, AluOp::a,"PRED_SETGE_INT")},
|
||||
{op2_pred_setne_int ,AluOp(2, 0, AluOp::a,"PRED_SETNE_INT")},
|
||||
{op2_kille_int ,AluOp(2, 0, AluOp::a,"KILLE_INT")},
|
||||
{op2_killgt_int ,AluOp(2, 0, AluOp::a,"KILLGT_INT")},
|
||||
{op2_killge_int ,AluOp(2, 0, AluOp::a,"KILLGE_INT")},
|
||||
{op2_killne_int ,AluOp(2, 0, AluOp::a,"KILLNE_INT")},
|
||||
{op2_pred_sete_push_int ,AluOp(2, 0, AluOp::a,"PRED_SETE_PUSH_INT")},
|
||||
{op2_pred_setgt_push_int ,AluOp(2, 0, AluOp::a,"PRED_SETGT_PUSH_INT")},
|
||||
{op2_pred_setge_push_int ,AluOp(2, 0, AluOp::a,"PRED_SETGE_PUSH_INT")},
|
||||
{op2_pred_setne_push_int ,AluOp(2, 0, AluOp::a,"PRED_SETNE_PUSH_INT")},
|
||||
{op2_pred_setlt_push_int ,AluOp(2, 0, AluOp::a,"PRED_SETLT_PUSH_INT")},
|
||||
{op2_pred_setle_push_int ,AluOp(2, 0, AluOp::a,"PRED_SETLE_PUSH_INT")},
|
||||
{op2_addc_uint ,AluOp(2, 0, AluOp::a,"ADDC_UINT")},
|
||||
{op2_subb_uint ,AluOp(2, 0, AluOp::a,"SUBB_UINT")},
|
||||
{op2_set_mode ,AluOp(2, 0, AluOp::a,"SET_MODE")},
|
||||
{op2_set_lds_size ,AluOp(2, 0, AluOp::a,"SET_LDS_SIZE")},
|
||||
{op2_mullo_int ,AluOp(2, 0, AluOp::t,"MULLO_INT")},
|
||||
{op2_mulhi_int ,AluOp(2, 0, AluOp::t,"MULHI_INT")},
|
||||
{op2_mullo_uint ,AluOp(2, 0, AluOp::t,"MULLO_UINT")},
|
||||
{op2_mulhi_uint ,AluOp(2, 0, AluOp::t,"MULHI_UINT")},
|
||||
{op2_dot_ieee ,AluOp(2, 1, AluOp::v,"DOT_IEEE")},
|
||||
{op2_mulhi_uint24 ,AluOp(2, 0, AluOp::v,"MULHI_UINT24")},
|
||||
{op2_mul_uint24 ,AluOp(2, 0, AluOp::v,"MUL_UINT24")},
|
||||
{op2_sete_64 ,AluOp(2, 1, AluOp::v,"SETE_64")},
|
||||
{op2_setne_64 ,AluOp(2, 1, AluOp::v,"SETNE_64")},
|
||||
{op2_setgt_64 ,AluOp(2, 1, AluOp::v,"SETGT_64")},
|
||||
{op2_setge_64 ,AluOp(2, 1, AluOp::v,"SETGE_64")},
|
||||
{op2_min_64 ,AluOp(2, 1, AluOp::v,"MIN_64")},
|
||||
{op2_max_64 ,AluOp(2, 1, AluOp::v,"MAX_64")},
|
||||
{op2_dot4 ,AluOp(2, 1, AluOp::v,"DOT4")},
|
||||
{op2_dot4_ieee ,AluOp(2, 1, AluOp::v,"DOT4_IEEE")},
|
||||
{op2_cube ,AluOp(2, 1, AluOp::v,"CUBE")},
|
||||
{op2_pred_setgt_64 ,AluOp(2, 1, AluOp::v,"PRED_SETGT_64")},
|
||||
{op2_pred_sete_64 ,AluOp(2, 1, AluOp::v,"PRED_SETE_64")},
|
||||
{op2_pred_setge_64 ,AluOp(2, 1, AluOp::v,"PRED_SETGE_64")},
|
||||
{OP2V_MUL_64 ,AluOp(2, 1, AluOp::v,"MUL_64")},
|
||||
{op2_add_64 ,AluOp(2, 1, AluOp::v,"ADD_64")},
|
||||
{op2_sad_accum_prev_uint ,AluOp(2, 0, AluOp::v,"SAD_ACCUM_PREV_UINT")},
|
||||
{op2_dot ,AluOp(2, 1, AluOp::v,"DOT")},
|
||||
{op1_mul_prev ,AluOp(2, 1, AluOp::v,"MUL_PREV")},
|
||||
{op1_mul_ieee_prev ,AluOp(2, 1, AluOp::v,"MUL_IEEE_PREV")},
|
||||
{op1_add_prev ,AluOp(2, 1, AluOp::v,"ADD_PREV")},
|
||||
{op2_muladd_prev ,AluOp(2, 1, AluOp::v,"MULADD_PREV")},
|
||||
{op2_muladd_ieee_prev ,AluOp(2, 1, AluOp::v,"MULADD_IEEE_PREV")},
|
||||
{op2_interp_xy ,AluOp(2, 1, AluOp::v,"INTERP_XY")},
|
||||
{op2_interp_zw ,AluOp(2, 1, AluOp::v,"INTERP_ZW")},
|
||||
{op2_interp_x ,AluOp(2, 1, AluOp::v,"INTERP_X")},
|
||||
{op2_interp_z ,AluOp(2, 1, AluOp::v,"INTERP_Z")},
|
||||
{op2_add ,AluOp(2, 1, AluOp::a, AluOp::a,"ADD")},
|
||||
{op2_bfm_int ,AluOp(2, 0, AluOp::v, AluOp::v,"BFM_INT")},
|
||||
{op2_mul ,AluOp(2, 1, AluOp::a, AluOp::a,"MUL")},
|
||||
{op2_mul_ieee ,AluOp(2, 1, AluOp::a, AluOp::a,"MUL_IEEE")},
|
||||
{op2_max ,AluOp(2, 1, AluOp::a, AluOp::a,"MAX")},
|
||||
{op2_min ,AluOp(2, 1, AluOp::a, AluOp::a,"MIN")},
|
||||
{op2_max_dx10 ,AluOp(2, 1, AluOp::a, AluOp::a,"MAX_DX10")},
|
||||
{op2_min_dx10 ,AluOp(2, 1, AluOp::a, AluOp::a,"MIN_DX10")},
|
||||
{op2_sete ,AluOp(2, 1, AluOp::a, AluOp::a,"SETE")},
|
||||
{op2_setgt ,AluOp(2, 1, AluOp::a, AluOp::a,"SETGT")},
|
||||
{op2_setge ,AluOp(2, 1, AluOp::a, AluOp::a,"SETGE")},
|
||||
{op2_setne ,AluOp(2, 1, AluOp::a, AluOp::a,"SETNE")},
|
||||
{op2_sete_dx10 ,AluOp(2, 1, AluOp::a, AluOp::a,"SETE_DX10")},
|
||||
{op2_setgt_dx10 ,AluOp(2, 1, AluOp::a, AluOp::a,"SETGT_DX10")},
|
||||
{op2_setge_dx10 ,AluOp(2, 1, AluOp::a, AluOp::a,"SETGE_DX10")},
|
||||
{op2_setne_dx10 ,AluOp(2, 1, AluOp::a, AluOp::a,"SETNE_DX10")},
|
||||
{op2_ashr_int ,AluOp(2, 0, AluOp::a, AluOp::a,"ASHR_INT")},
|
||||
{op2_lshr_int ,AluOp(2, 0, AluOp::a, AluOp::a,"LSHR_INT")},
|
||||
{op2_lshl_int ,AluOp(2, 0, AluOp::a, AluOp::a,"LSHL_INT")},
|
||||
{op2_mul_64 ,AluOp(2, 1, AluOp::a, AluOp::a,"MUL_64")},
|
||||
{op2_pred_setgt_uint ,AluOp(2, 0, AluOp::a, AluOp::a,"PRED_SETGT_UINT")},
|
||||
{op2_pred_setge_uint ,AluOp(2, 0, AluOp::a, AluOp::a,"PRED_SETGE_UINT")},
|
||||
{op2_pred_sete ,AluOp(2, 1, AluOp::a, AluOp::a,"PRED_SETE")},
|
||||
{op2_pred_setgt ,AluOp(2, 1, AluOp::a, AluOp::a,"PRED_SETGT")},
|
||||
{op2_pred_setge ,AluOp(2, 1, AluOp::a, AluOp::a,"PRED_SETGE")},
|
||||
{op2_pred_setne ,AluOp(2, 1, AluOp::a, AluOp::a,"PRED_SETNE")},
|
||||
{op2_pred_set_pop ,AluOp(2, 1, AluOp::a, AluOp::a,"PRED_SET_POP")},
|
||||
{op2_pred_sete_push ,AluOp(2, 1, AluOp::a, AluOp::a,"PRED_SETE_PUSH")},
|
||||
{op2_pred_setgt_push ,AluOp(2, 1, AluOp::a, AluOp::a,"PRED_SETGT_PUSH")},
|
||||
{op2_pred_setge_push ,AluOp(2, 1, AluOp::a, AluOp::a,"PRED_SETGE_PUSH")},
|
||||
{op2_pred_setne_push ,AluOp(2, 1, AluOp::a, AluOp::a,"PRED_SETNE_PUSH")},
|
||||
{op2_kille ,AluOp(2, 1, AluOp::a, AluOp::a,"KILLE")},
|
||||
{op2_killgt ,AluOp(2, 1, AluOp::a, AluOp::a,"KILLGT")},
|
||||
{op2_killge ,AluOp(2, 1, AluOp::a, AluOp::a,"KILLGE")},
|
||||
{op2_killne ,AluOp(2, 1, AluOp::a, AluOp::a,"KILLNE")},
|
||||
{op2_and_int ,AluOp(2, 0, AluOp::a, AluOp::a,"AND_INT")},
|
||||
{op2_or_int ,AluOp(2, 0, AluOp::a, AluOp::a,"OR_INT")},
|
||||
{op2_xor_int ,AluOp(2, 0, AluOp::a, AluOp::a,"XOR_INT")},
|
||||
{op2_add_int ,AluOp(2, 0, AluOp::a, AluOp::a,"ADD_INT")},
|
||||
{op2_sub_int ,AluOp(2, 0, AluOp::a, AluOp::a,"SUB_INT")},
|
||||
{op2_max_int ,AluOp(2, 0, AluOp::a, AluOp::a,"MAX_INT")},
|
||||
{op2_min_int ,AluOp(2, 0, AluOp::a, AluOp::a,"MIN_INT")},
|
||||
{op2_max_uint ,AluOp(2, 0, AluOp::a, AluOp::a,"MAX_UINT")},
|
||||
{op2_min_uint ,AluOp(2, 0, AluOp::a, AluOp::a,"MIN_UINT")},
|
||||
{op2_sete_int ,AluOp(2, 0, AluOp::a, AluOp::a,"SETE_INT")},
|
||||
{op2_setgt_int ,AluOp(2, 0, AluOp::a, AluOp::a,"SETGT_INT")},
|
||||
{op2_setge_int ,AluOp(2, 0, AluOp::a, AluOp::a,"SETGE_INT")},
|
||||
{op2_setne_int ,AluOp(2, 0, AluOp::a, AluOp::a,"SETNE_INT")},
|
||||
{op2_setgt_uint ,AluOp(2, 0, AluOp::a, AluOp::a,"SETGT_UINT")},
|
||||
{op2_setge_uint ,AluOp(2, 0, AluOp::a, AluOp::a,"SETGE_UINT")},
|
||||
{op2_killgt_uint ,AluOp(2, 0, AluOp::a, AluOp::a,"KILLGT_UINT")},
|
||||
{op2_killge_uint ,AluOp(2, 0, AluOp::a, AluOp::a,"KILLGE_UINT")},
|
||||
{op2_prede_int ,AluOp(2, 0, AluOp::a, AluOp::a,"PREDE_INT")},
|
||||
{op2_pred_setgt_int ,AluOp(2, 0, AluOp::a, AluOp::a,"PRED_SETGT_INT")},
|
||||
{op2_pred_setge_int ,AluOp(2, 0, AluOp::a, AluOp::a,"PRED_SETGE_INT")},
|
||||
{op2_pred_setne_int ,AluOp(2, 0, AluOp::a, AluOp::a,"PRED_SETNE_INT")},
|
||||
{op2_kille_int ,AluOp(2, 0, AluOp::a, AluOp::a,"KILLE_INT")},
|
||||
{op2_killgt_int ,AluOp(2, 0, AluOp::a, AluOp::a,"KILLGT_INT")},
|
||||
{op2_killge_int ,AluOp(2, 0, AluOp::a, AluOp::a,"KILLGE_INT")},
|
||||
{op2_killne_int ,AluOp(2, 0, AluOp::a, AluOp::a,"KILLNE_INT")},
|
||||
{op2_pred_sete_push_int ,AluOp(2, 0, AluOp::a, AluOp::a,"PRED_SETE_PUSH_INT")},
|
||||
{op2_pred_setgt_push_int ,AluOp(2, 0, AluOp::a, AluOp::a,"PRED_SETGT_PUSH_INT")},
|
||||
{op2_pred_setge_push_int ,AluOp(2, 0, AluOp::a, AluOp::a,"PRED_SETGE_PUSH_INT")},
|
||||
{op2_pred_setne_push_int ,AluOp(2, 0, AluOp::a, AluOp::a,"PRED_SETNE_PUSH_INT")},
|
||||
{op2_pred_setlt_push_int ,AluOp(2, 0, AluOp::a, AluOp::a,"PRED_SETLT_PUSH_INT")},
|
||||
{op2_pred_setle_push_int ,AluOp(2, 0, AluOp::a, AluOp::a,"PRED_SETLE_PUSH_INT")},
|
||||
{op2_addc_uint ,AluOp(2, 0, AluOp::a, AluOp::a,"ADDC_UINT")},
|
||||
{op2_subb_uint ,AluOp(2, 0, AluOp::a, AluOp::a,"SUBB_UINT")},
|
||||
{op2_set_mode ,AluOp(2, 0, AluOp::a, AluOp::a,"SET_MODE")},
|
||||
{op2_set_lds_size ,AluOp(2, 0, AluOp::a, AluOp::a,"SET_LDS_SIZE")},
|
||||
{op2_mullo_int ,AluOp(2, 0, AluOp::t, AluOp::t,"MULLO_INT")},
|
||||
{op2_mulhi_int ,AluOp(2, 0, AluOp::t, AluOp::t,"MULHI_INT")},
|
||||
{op2_mullo_uint ,AluOp(2, 0, AluOp::t, AluOp::t,"MULLO_UINT")},
|
||||
{op2_mulhi_uint ,AluOp(2, 0, AluOp::t, AluOp::t,"MULHI_UINT")},
|
||||
{op2_dot_ieee ,AluOp(2, 1, AluOp::v, AluOp::v,"DOT_IEEE")},
|
||||
{op2_mulhi_uint24 ,AluOp(2, 0, AluOp::v, AluOp::v,"MULHI_UINT24")},
|
||||
{op2_mul_uint24 ,AluOp(2, 0, AluOp::v, AluOp::v,"MUL_UINT24")},
|
||||
{op2_sete_64 ,AluOp(2, 1, AluOp::v, AluOp::v,"SETE_64")},
|
||||
{op2_setne_64 ,AluOp(2, 1, AluOp::v, AluOp::v,"SETNE_64")},
|
||||
{op2_setgt_64 ,AluOp(2, 1, AluOp::v, AluOp::v,"SETGT_64")},
|
||||
{op2_setge_64 ,AluOp(2, 1, AluOp::v, AluOp::v,"SETGE_64")},
|
||||
{op2_min_64 ,AluOp(2, 1, AluOp::v, AluOp::v,"MIN_64")},
|
||||
{op2_max_64 ,AluOp(2, 1, AluOp::v, AluOp::v,"MAX_64")},
|
||||
{op2_dot4 ,AluOp(2, 1, AluOp::v, AluOp::v,"DOT4")},
|
||||
{op2_dot4_ieee ,AluOp(2, 1, AluOp::v, AluOp::v,"DOT4_IEEE")},
|
||||
{op2_cube ,AluOp(2, 1, AluOp::v, AluOp::v,"CUBE")},
|
||||
{op2_pred_setgt_64 ,AluOp(2, 1, AluOp::v, AluOp::v,"PRED_SETGT_64")},
|
||||
{op2_pred_sete_64 ,AluOp(2, 1, AluOp::v, AluOp::v,"PRED_SETE_64")},
|
||||
{op2_pred_setge_64 ,AluOp(2, 1, AluOp::v, AluOp::v,"PRED_SETGE_64")},
|
||||
{OP2V_MUL_64 ,AluOp(2, 1, AluOp::v, AluOp::v,"MUL_64")},
|
||||
{op2_add_64 ,AluOp(2, 1, AluOp::v, AluOp::v,"ADD_64")},
|
||||
{op2_sad_accum_prev_uint ,AluOp(2, 0, AluOp::v, AluOp::v,"SAD_ACCUM_PREV_UINT")},
|
||||
{op2_dot ,AluOp(2, 1, AluOp::v, AluOp::v,"DOT")},
|
||||
{op1_mul_prev ,AluOp(2, 1, AluOp::v, AluOp::v,"MUL_PREV")},
|
||||
{op1_mul_ieee_prev ,AluOp(2, 1, AluOp::v, AluOp::v,"MUL_IEEE_PREV")},
|
||||
{op1_add_prev ,AluOp(2, 1, AluOp::v, AluOp::v,"ADD_PREV")},
|
||||
{op2_muladd_prev ,AluOp(2, 1, AluOp::v, AluOp::v,"MULADD_PREV")},
|
||||
{op2_muladd_ieee_prev ,AluOp(2, 1, AluOp::v, AluOp::v,"MULADD_IEEE_PREV")},
|
||||
{op2_interp_xy ,AluOp(2, 1, AluOp::v, AluOp::v,"INTERP_XY")},
|
||||
{op2_interp_zw ,AluOp(2, 1, AluOp::v, AluOp::v,"INTERP_ZW")},
|
||||
{op2_interp_x ,AluOp(2, 1, AluOp::v, AluOp::v,"INTERP_X")},
|
||||
{op2_interp_z ,AluOp(2, 1, AluOp::v, AluOp::v,"INTERP_Z")},
|
||||
|
||||
{op3_bfe_uint ,AluOp(3, 0, AluOp::v,"BFE_UINT")},
|
||||
{op3_bfe_int ,AluOp(3, 0, AluOp::v,"BFE_INT")},
|
||||
{op3_bfi_int ,AluOp(3, 0, AluOp::v,"BFI_INT")},
|
||||
{op3_fma ,AluOp(3, 1, AluOp::v,"FMA")},
|
||||
{op3_cndne_64 ,AluOp(3, 1, AluOp::v,"CNDNE_64")},
|
||||
{op3_fma_64 ,AluOp(3, 1, AluOp::v,"FMA_64")},
|
||||
{op3_lerp_uint ,AluOp(3, 0, AluOp::v,"LERP_UINT")},
|
||||
{op3_bit_align_int ,AluOp(3, 0, AluOp::v,"BIT_ALIGN_INT")},
|
||||
{op3_byte_align_int ,AluOp(3, 0, AluOp::v,"BYTE_ALIGN_INT")},
|
||||
{op3_sad_accum_uint ,AluOp(3, 0, AluOp::v,"SAD_ACCUM_UINT")},
|
||||
{op3_sad_accum_hi_uint ,AluOp(3, 0, AluOp::v,"SAD_ACCUM_HI_UINT")},
|
||||
{op3_muladd_uint24 ,AluOp(3, 0, AluOp::v,"MULADD_UINT24")},
|
||||
{op3_lds_idx_op ,AluOp(3, 0, AluOp::x,"LDS_IDX_OP")},
|
||||
{op3_muladd ,AluOp(3, 1, AluOp::a,"MULADD")},
|
||||
{op3_muladd_m2 ,AluOp(3, 1, AluOp::a,"MULADD_M2")},
|
||||
{op3_muladd_m4 ,AluOp(3, 1, AluOp::a,"MULADD_M4")},
|
||||
{op3_muladd_d2 ,AluOp(3, 1, AluOp::a,"MULADD_D2")},
|
||||
{op3_muladd_ieee ,AluOp(3, 1, AluOp::a,"MULADD_IEEE")},
|
||||
{op3_cnde ,AluOp(3, 1, AluOp::a,"CNDE")},
|
||||
{op3_cndgt ,AluOp(3, 1, AluOp::a,"CNDGT")},
|
||||
{op3_cndge ,AluOp(3, 1, AluOp::a,"CNDGE")},
|
||||
{op3_cnde_int ,AluOp(3, 0, AluOp::a,"CNDE_INT")},
|
||||
{op3_cndgt_int ,AluOp(3, 0, AluOp::a,"CNDGT_INT")},
|
||||
{op3_cndge_int ,AluOp(3, 0, AluOp::a,"CNDGE_INT")},
|
||||
{op3_mul_lit ,AluOp(3, 1, AluOp::t,"MUL_LIT")}
|
||||
{op3_bfe_uint ,AluOp(3, 0, AluOp::v, AluOp::v,"BFE_UINT")},
|
||||
{op3_bfe_int ,AluOp(3, 0, AluOp::v, AluOp::v,"BFE_INT")},
|
||||
{op3_bfi_int ,AluOp(3, 0, AluOp::v, AluOp::v,"BFI_INT")},
|
||||
{op3_fma ,AluOp(3, 1, AluOp::v, AluOp::v,"FMA")},
|
||||
{op3_cndne_64 ,AluOp(3, 1, AluOp::v, AluOp::v,"CNDNE_64")},
|
||||
{op3_fma_64 ,AluOp(3, 1, AluOp::v, AluOp::v,"FMA_64")},
|
||||
{op3_lerp_uint ,AluOp(3, 0, AluOp::v, AluOp::v,"LERP_UINT")},
|
||||
{op3_bit_align_int ,AluOp(3, 0, AluOp::v, AluOp::v,"BIT_ALIGN_INT")},
|
||||
{op3_byte_align_int ,AluOp(3, 0, AluOp::v, AluOp::v,"BYTE_ALIGN_INT")},
|
||||
{op3_sad_accum_uint ,AluOp(3, 0, AluOp::v, AluOp::v,"SAD_ACCUM_UINT")},
|
||||
{op3_sad_accum_hi_uint ,AluOp(3, 0, AluOp::v, AluOp::v,"SAD_ACCUM_HI_UINT")},
|
||||
{op3_muladd_uint24 ,AluOp(3, 0, AluOp::v, AluOp::v,"MULADD_UINT24")},
|
||||
{op3_lds_idx_op ,AluOp(3, 0, AluOp::x, AluOp::x,"LDS_IDX_OP")},
|
||||
{op3_muladd ,AluOp(3, 1, AluOp::a, AluOp::a,"MULADD")},
|
||||
{op3_muladd_m2 ,AluOp(3, 1, AluOp::a, AluOp::a,"MULADD_M2")},
|
||||
{op3_muladd_m4 ,AluOp(3, 1, AluOp::a, AluOp::a,"MULADD_M4")},
|
||||
{op3_muladd_d2 ,AluOp(3, 1, AluOp::a, AluOp::a,"MULADD_D2")},
|
||||
{op3_muladd_ieee ,AluOp(3, 1, AluOp::a, AluOp::a,"MULADD_IEEE")},
|
||||
{op3_cnde ,AluOp(3, 1, AluOp::a, AluOp::a,"CNDE")},
|
||||
{op3_cndgt ,AluOp(3, 1, AluOp::a, AluOp::a,"CNDGT")},
|
||||
{op3_cndge ,AluOp(3, 1, AluOp::a, AluOp::a,"CNDGE")},
|
||||
{op3_cnde_int ,AluOp(3, 0, AluOp::a, AluOp::a,"CNDE_INT")},
|
||||
{op3_cndgt_int ,AluOp(3, 0, AluOp::a, AluOp::a,"CNDGT_INT")},
|
||||
{op3_cndge_int ,AluOp(3, 0, AluOp::a, AluOp::a,"CNDGE_INT")},
|
||||
{op3_mul_lit ,AluOp(3, 1, AluOp::t, AluOp::t,"MUL_LIT")}
|
||||
};
|
||||
|
||||
const std::map<AluInlineConstants, AluInlineConstantDescr> alu_src_const = {
|
||||
|
|
|
|||
|
|
@ -312,18 +312,19 @@ struct AluOp {
|
|||
static constexpr int t = 16;
|
||||
static constexpr int a = 31;
|
||||
|
||||
AluOp(int ns, int f, int um, const char *n):
|
||||
nsrc(ns), is_float(f), unit_mask(um), name(n)
|
||||
AluOp(int ns, int f, int um, int um_eg, const char *n):
|
||||
nsrc(ns), is_float(f), unit_mask(um), unit_mask_eg(um_eg), name(n)
|
||||
{
|
||||
}
|
||||
|
||||
bool can_channel(int flags) const {
|
||||
return flags & unit_mask;
|
||||
bool can_channel(int flags, bool eg) const {
|
||||
return flags & (eg ? unit_mask_eg : unit_mask);
|
||||
}
|
||||
|
||||
int nsrc: 4;
|
||||
int is_float:1;
|
||||
int unit_mask: 5;
|
||||
int unit_mask_eg: 5;
|
||||
const char *name;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -1227,6 +1227,21 @@ bool AluInstr::from_nir(nir_alu_instr *alu, Shader& shader)
|
|||
;
|
||||
}
|
||||
} else {
|
||||
if (shader.chip_class() == ISA_CC_EVERGREEN) {
|
||||
switch (alu->op) {
|
||||
case nir_op_f2i32: return emit_alu_f2i32_or_u32_eg(*alu, op1_flt_to_int, shader);
|
||||
case nir_op_f2u32: return emit_alu_f2i32_or_u32_eg(*alu, op1_flt_to_uint, shader);
|
||||
default:
|
||||
;
|
||||
}
|
||||
} else {
|
||||
switch (alu->op) {
|
||||
case nir_op_f2i32: return emit_alu_trans_op1_eg(*alu, op1_flt_to_int, shader);
|
||||
case nir_op_f2u32: return emit_alu_trans_op1_eg(*alu, op1_flt_to_uint, shader);
|
||||
default:
|
||||
;
|
||||
}
|
||||
}
|
||||
switch (alu->op) {
|
||||
case nir_op_fcos_amd: return emit_alu_trans_op1_eg(*alu, op1_cos, shader);
|
||||
case nir_op_fexp2: return emit_alu_trans_op1_eg(*alu, op1_exp_ieee, shader);
|
||||
|
|
@ -1240,8 +1255,6 @@ bool AluInstr::from_nir(nir_alu_instr *alu, Shader& shader)
|
|||
case nir_op_imul: return emit_alu_trans_op2_eg(*alu, op2_mullo_int, shader);
|
||||
case nir_op_imul_high: return emit_alu_trans_op2_eg(*alu, op2_mulhi_int, shader);
|
||||
case nir_op_umul_high: return emit_alu_trans_op2_eg(*alu, op2_mulhi_uint, shader);
|
||||
case nir_op_f2i32: return emit_alu_f2i32_or_u32_eg(*alu, op1_flt_to_int, shader);
|
||||
case nir_op_f2u32: return emit_alu_f2i32_or_u32_eg(*alu, op1_flt_to_uint, shader);
|
||||
default:
|
||||
;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -42,8 +42,12 @@ bool AluGroup::add_instruction(AluInstr *instr)
|
|||
if (m_has_lds_op && instr->has_lds_access())
|
||||
return false;
|
||||
|
||||
if (instr->has_alu_flag(alu_is_trans) && add_trans_instructions(instr))
|
||||
return true;
|
||||
if (instr->has_alu_flag(alu_is_trans)) {
|
||||
auto opinfo = alu_ops.find(instr->opcode());
|
||||
assert(opinfo->second.can_channel(AluOp::t, s_eg_t_slot_handling));
|
||||
if (add_trans_instructions(instr))
|
||||
return true;
|
||||
}
|
||||
|
||||
if (add_vec_instructions(instr)) {
|
||||
instr->set_parent_group(this);
|
||||
|
|
@ -54,7 +58,7 @@ bool AluGroup::add_instruction(AluInstr *instr)
|
|||
assert(opinfo != alu_ops.end());
|
||||
|
||||
if (s_max_slots > 4 &&
|
||||
opinfo->second.can_channel(AluOp::t) &&
|
||||
opinfo->second.can_channel(AluOp::t, s_eg_t_slot_handling) &&
|
||||
add_trans_instructions(instr)) {
|
||||
instr->set_parent_group(this);
|
||||
return true;
|
||||
|
|
@ -78,8 +82,10 @@ bool AluGroup::add_trans_instructions(AluInstr *instr)
|
|||
auto opinfo = alu_ops.find(instr->opcode());
|
||||
assert(opinfo != alu_ops.end());
|
||||
|
||||
if (!opinfo->second.can_channel(AluOp::t))
|
||||
if (!opinfo->second.can_channel(AluOp::t, s_eg_t_slot_handling)) {
|
||||
std::cerr << *instr << ": t-slot not supported ("<< s_eg_t_slot_handling << ")\n";
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
/* if we schedule a non-trans instr into the trans slot, we have to make
|
||||
|
|
@ -373,15 +379,19 @@ AluInstr::SrcValues AluGroup::get_kconsts() const
|
|||
|
||||
void AluGroup::set_chipclass(r600_chip_class chip_class)
|
||||
{
|
||||
s_eg_t_slot_handling = false;
|
||||
switch (chip_class) {
|
||||
case ISA_CC_CAYMAN:
|
||||
s_max_slots = 4;
|
||||
break;
|
||||
case ISA_CC_EVERGREEN:
|
||||
s_eg_t_slot_handling = true;
|
||||
FALLTHROUGH;
|
||||
default:
|
||||
s_max_slots = 5;
|
||||
}
|
||||
}
|
||||
|
||||
int AluGroup::s_max_slots = 5;
|
||||
|
||||
bool AluGroup::s_eg_t_slot_handling = false;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -99,6 +99,7 @@ private:
|
|||
AluReadportReservation m_readports_evaluator;
|
||||
|
||||
static int s_max_slots;
|
||||
static bool s_eg_t_slot_handling;
|
||||
|
||||
PRegister m_addr_used{nullptr};
|
||||
|
||||
|
|
|
|||
|
|
@ -148,7 +148,7 @@ public:
|
|||
|
||||
class BlockSheduler {
|
||||
public:
|
||||
BlockSheduler();
|
||||
BlockSheduler( bool eg_t_slot_handling);
|
||||
void run(Shader *shader);
|
||||
|
||||
void finalize();
|
||||
|
|
@ -218,6 +218,7 @@ private:
|
|||
|
||||
int m_lds_addr_count{0};
|
||||
int m_alu_groups_schduled{0};
|
||||
bool m_eg_t_slot_handling;
|
||||
|
||||
};
|
||||
|
||||
|
|
@ -236,7 +237,7 @@ Shader *schedule(Shader *original)
|
|||
// to be able to re-start scheduling
|
||||
|
||||
auto scheduled_shader = original;
|
||||
BlockSheduler s;
|
||||
BlockSheduler s(original->chip_class() >= ISA_CC_EVERGREEN);
|
||||
s.run(scheduled_shader);
|
||||
s.finalize();
|
||||
|
||||
|
|
@ -250,12 +251,13 @@ Shader *schedule(Shader *original)
|
|||
return scheduled_shader;
|
||||
}
|
||||
|
||||
BlockSheduler::BlockSheduler():
|
||||
BlockSheduler::BlockSheduler(bool eg_t_slot_handling):
|
||||
current_shed(sched_alu),
|
||||
m_last_pos(nullptr),
|
||||
m_last_pixel(nullptr),
|
||||
m_last_param(nullptr),
|
||||
m_current_block(nullptr)
|
||||
m_current_block(nullptr),
|
||||
m_eg_t_slot_handling(eg_t_slot_handling)
|
||||
{
|
||||
}
|
||||
|
||||
|
|
@ -820,7 +822,8 @@ bool BlockSheduler::collect_ready_alu_vec(std::list<AluInstr *>& ready, std::lis
|
|||
else if (AluGroup::has_t()) {
|
||||
auto opinfo = alu_ops.find((*i)->opcode());
|
||||
assert(opinfo != alu_ops.end());
|
||||
if (opinfo->second.can_channel(AluOp::t) && !(*i)->indirect_addr().first)
|
||||
if (opinfo->second.can_channel(AluOp::t, m_eg_t_slot_handling) &&
|
||||
!(*i)->indirect_addr().first)
|
||||
priority = -1;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue