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amd,radeonsi: add GFX11 packed context registers helpers to common code
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38187>
This commit is contained in:
Samuel Pitoiset
Marge Bot
parent
a6ca6bcabf
commit
3c5ec268ec
2 changed files with 53 additions and 38 deletions
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@ -169,6 +169,46 @@ struct ac_buffered_sh_regs {
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ac_cmdbuf_emit(0); /* unused */ \
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} while (0)
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/* GFX11 generic packet building helpers for buffered SH registers. Don't use these directly. */
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#define ac_gfx11_push_reg(reg, value, prefix_name, buffer, reg_count) \
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do { \
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unsigned __i = (reg_count)++; \
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assert((reg) >= prefix_name##_REG_OFFSET && (reg) < prefix_name##_REG_END); \
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assert(__i / 2 < ARRAY_SIZE(buffer)); \
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buffer[__i / 2].reg_offset[__i % 2] = ((reg) - prefix_name##_REG_OFFSET) >> 2; \
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buffer[__i / 2].reg_value[__i % 2] = value; \
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} while (0)
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/* GFX11 packet building helpers for SET_CONTEXT_REG_PAIRS_PACKED.
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* Registers are buffered on the stack and then copied to the command buffer at the end.
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*/
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#define ac_gfx11_begin_packed_context_regs() \
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struct ac_gfx11_reg_pair __cs_context_regs[50]; \
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unsigned __cs_context_reg_count = 0;
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#define ac_gfx11_set_context_reg(reg, value) \
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ac_gfx11_push_reg(reg, value, SI_CONTEXT, __cs_context_regs, __cs_context_reg_count)
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#define ac_gfx11_end_packed_context_regs() \
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do { \
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if (__cs_context_reg_count >= 2) { \
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/* Align the count to 2 by duplicating the first register. */ \
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if (__cs_context_reg_count % 2 == 1) { \
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ac_gfx11_set_context_reg(SI_CONTEXT_REG_OFFSET + __cs_context_regs[0].reg_offset[0] * 4, \
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__cs_context_regs[0].reg_value[0]); \
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} \
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assert(__cs_context_reg_count % 2 == 0); \
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unsigned __num_dw = (__cs_context_reg_count / 2) * 3; \
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ac_cmdbuf_emit(PKT3(PKT3_SET_CONTEXT_REG_PAIRS_PACKED, __num_dw, 0) | PKT3_RESET_FILTER_CAM_S(1)); \
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ac_cmdbuf_emit(__cs_context_reg_count); \
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ac_cmdbuf_emit_array(__cs_context_regs, __num_dw); \
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} else if (__cs_context_reg_count == 1) { \
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ac_cmdbuf_emit(PKT3(PKT3_SET_CONTEXT_REG, 1, 0)); \
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ac_cmdbuf_emit(__cs_context_regs[0].reg_offset[0]); \
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ac_cmdbuf_emit(__cs_context_regs[0].reg_value[0]); \
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} \
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} while (0)
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/* GFX12 generic packet building helpers for PAIRS packets. Don't use these directly. */
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/* Reserved 1 DWORD to emit the packet header when the sequence ends. */
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@ -287,19 +287,11 @@
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ac_cmdbuf_set_privileged_config_reg(reg, value)
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/* GFX11 generic packet building helpers for buffered SH registers. Don't use these directly. */
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#define gfx11_push_reg(reg, value, prefix_name, buffer, reg_count) do { \
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unsigned __i = (reg_count)++; \
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assert((reg) >= prefix_name##_REG_OFFSET && (reg) < prefix_name##_REG_END); \
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assert(__i / 2 < ARRAY_SIZE(buffer)); \
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buffer[__i / 2].reg_offset[__i % 2] = ((reg) - prefix_name##_REG_OFFSET) >> 2; \
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buffer[__i / 2].reg_value[__i % 2] = value; \
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} while (0)
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#define gfx11_opt_push_reg(reg, reg_enum, value, prefix_name, buffer, reg_count) do { \
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unsigned __value = value; \
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if (!BITSET_TEST(sctx->tracked_regs.reg_saved_mask, (reg_enum)) || \
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sctx->tracked_regs.reg_value[reg_enum] != __value) { \
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gfx11_push_reg(reg, __value, prefix_name, buffer, reg_count); \
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ac_gfx11_push_reg(reg, __value, prefix_name, buffer, reg_count); \
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BITSET_SET(sctx->tracked_regs.reg_saved_mask, (reg_enum)); \
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sctx->tracked_regs.reg_value[reg_enum] = __value; \
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} \
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@ -318,10 +310,10 @@
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sctx->tracked_regs.reg_value[(reg_enum) + 1] != __v2 || \
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sctx->tracked_regs.reg_value[(reg_enum) + 2] != __v3 || \
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sctx->tracked_regs.reg_value[(reg_enum) + 3] != __v4) { \
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gfx11_push_reg((reg), __v1, prefix_name, buffer, reg_count); \
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gfx11_push_reg((reg) + 4, __v2, prefix_name, buffer, reg_count); \
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gfx11_push_reg((reg) + 8, __v3, prefix_name, buffer, reg_count); \
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gfx11_push_reg((reg) + 12, __v4, prefix_name, buffer, reg_count); \
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ac_gfx11_push_reg((reg), __v1, prefix_name, buffer, reg_count); \
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ac_gfx11_push_reg((reg) + 4, __v2, prefix_name, buffer, reg_count); \
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ac_gfx11_push_reg((reg) + 8, __v3, prefix_name, buffer, reg_count); \
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ac_gfx11_push_reg((reg) + 12, __v4, prefix_name, buffer, reg_count); \
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BITSET_SET_RANGE_INSIDE_WORD(sctx->tracked_regs.reg_saved_mask, \
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(reg_enum), (reg_enum) + 3); \
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sctx->tracked_regs.reg_value[(reg_enum)] = __v1; \
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@ -333,12 +325,12 @@
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/* GFX11 packet building helpers for buffered SH registers. */
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#define gfx11_push_gfx_sh_reg(reg, value) \
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gfx11_push_reg(reg, value, SI_SH, sctx->buffered_gfx_sh_regs.gfx11.regs, \
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sctx->buffered_gfx_sh_regs.num)
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ac_gfx11_push_reg(reg, value, SI_SH, sctx->buffered_gfx_sh_regs.gfx11.regs, \
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sctx->buffered_gfx_sh_regs.num)
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#define gfx11_push_compute_sh_reg(reg, value) \
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gfx11_push_reg(reg, value, SI_SH, sctx->buffered_compute_sh_regs.gfx11.regs, \
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sctx->buffered_compute_sh_regs.num)
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ac_gfx11_push_reg(reg, value, SI_SH, sctx->buffered_compute_sh_regs.gfx11.regs, \
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sctx->buffered_compute_sh_regs.num)
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#define gfx11_opt_push_gfx_sh_reg(reg, reg_enum, value) \
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gfx11_opt_push_reg(reg, reg_enum, value, SI_SH, sctx->buffered_gfx_sh_regs.gfx11.regs, \
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@ -352,11 +344,10 @@
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* Registers are buffered on the stack and then copied to the command buffer at the end.
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*/
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#define gfx11_begin_packed_context_regs() \
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struct ac_gfx11_reg_pair __cs_context_regs[50]; \
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unsigned __cs_context_reg_count = 0;
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ac_gfx11_begin_packed_context_regs()
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#define gfx11_set_context_reg(reg, value) \
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gfx11_push_reg(reg, value, SI_CONTEXT, __cs_context_regs, __cs_context_reg_count)
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ac_gfx11_set_context_reg(reg, value)
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#define gfx11_opt_set_context_reg(reg, reg_enum, value) \
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gfx11_opt_push_reg(reg, reg_enum, value, SI_CONTEXT, __cs_context_regs, \
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@ -366,24 +357,8 @@
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gfx11_opt_push_reg4(reg, reg_enum, v1, v2, v3, v4, SI_CONTEXT, __cs_context_regs, \
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__cs_context_reg_count)
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#define gfx11_end_packed_context_regs() do { \
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if (__cs_context_reg_count >= 2) { \
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/* Align the count to 2 by duplicating the first register. */ \
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if (__cs_context_reg_count % 2 == 1) { \
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gfx11_set_context_reg(SI_CONTEXT_REG_OFFSET + __cs_context_regs[0].reg_offset[0] * 4, \
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__cs_context_regs[0].reg_value[0]); \
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} \
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assert(__cs_context_reg_count % 2 == 0); \
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unsigned __num_dw = (__cs_context_reg_count / 2) * 3; \
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radeon_emit(PKT3(PKT3_SET_CONTEXT_REG_PAIRS_PACKED, __num_dw, 0) | PKT3_RESET_FILTER_CAM_S(1)); \
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radeon_emit(__cs_context_reg_count); \
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radeon_emit_array(__cs_context_regs, __num_dw); \
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} else if (__cs_context_reg_count == 1) { \
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radeon_emit(PKT3(PKT3_SET_CONTEXT_REG, 1, 0)); \
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radeon_emit(__cs_context_regs[0].reg_offset[0]); \
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radeon_emit(__cs_context_regs[0].reg_value[0]); \
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} \
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} while (0)
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#define gfx11_end_packed_context_regs() \
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ac_gfx11_end_packed_context_regs()
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/* GFX12 generic packet building helpers for PAIRS packets. Don't use these directly. */
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