fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-06 13:48:06 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

anv: Fix Wa_14021821874, Wa_14018813551, Wa_14026600921

Browse source 
StackSizePerRay is the RTDispatchGlobals::AsyncStackSize and
DisableRTGlobalsKnownValues is to interpret how many Max BVH levels we
need to use. It's not relevant to Vulkan, since we have just 2 fixed BVH
levels.

Fixes: cb423ee6 ("anv: Fix Wa_14021821874, Wa_14018813551, Wa_14026600921")
Fixes: c1a44e8d ("anv: force StackIDControl value for Wa_14021821874")
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
(cherry picked from commit 7a627fa8f3)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41269>
This commit is contained in:
Sagar Ghuge 2026-04-16 15:20:46 -07:00 • committed by Eric Engestrom
parent 22a9e59685
commit 3c3c94532a
3 changed files with 31 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
.pick_status.json
View file

@ -3474,7 +3474,7 @@
"description": "anv: Fix Wa_14021821874, Wa_14018813551, Wa_14026600921",
"nominated": true,
"nomination_type": 2,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "cb423ee63608551e0d20d9f1fe36598c9e8883fa",
"notes": null

32
src/intel/compiler/brw/brw_rt.h
View file

@ -231,7 +231,26 @@ brw_rt_compute_scratch_layout(struct brw_rt_scratch_layout *layout,
assert(size % 64 == 0); /* Cache-line aligned */
assert(size < UINT32_MAX);
layout->ray_stack_start = size;
layout->ray_stack_stride = BRW_RT_ASYNC_STACK_STRIDE;
/* Wa_14021821874, Wa_14018813551, Wa_14026600921:
*
* StackIDControlOverride_RTGlobals = 0 (i.e. 2k)
* SetStackSizePerRay = 64 (64*64B)
* DisableRTGlobalsKnownValues = 1
*
* StackSizePerRay is the RTDispatchGlobals::AsyncStackSize and
* DisableRTGlobalsKnownValues is to interpret how many Max BVH levels we
* need to use. It's not relevant to Vulkan, since we have just 2 fixed BVH
* levels.
*/
if (intel_needs_workaround(devinfo, 14021821874) ||
intel_needs_workaround(devinfo, 14018813551) ||
intel_needs_workaround(devinfo, 14026600921)) {
layout->ray_stack_stride = 64 * 64;
} else {
layout->ray_stack_stride = BRW_RT_ASYNC_STACK_STRIDE;
}
size += num_stack_ids * layout->ray_stack_stride;
/* Finally, we place the SW stacks for the individual ray-tracing shader
@ -281,9 +300,14 @@ brw_rt_ray_queries_stack_ids_per_dss(const struct intel_device_info *devinfo)
/* Wa_14021821874, Wa_14018813551, Wa_14026600921:
*
* "StackIDControlOverride_RTGlobals = 0 (i.e. 2k)". We
* already set stack size per ray to 64 in brw_nir_lower_rt_intrinsics
* as the workaround also requires.
* StackIDControlOverride_RTGlobals = 0 (i.e. 2k)
* SetStackSizePerRay = 64 (64*64B)
* DisableRTGlobalsKnownValues = 1
*
* StackSizePerRay is the RTDispatchGlobals::AsyncStackSize and
* DisableRTGlobalsKnownValues is to interpret how many Max BVH levels we
* need to use. It's not relevant to Vulkan, since we have just 2 fixed BVH
* levels.
*/
if (intel_needs_workaround(devinfo, 14021821874) ||
intel_needs_workaround(devinfo, 14018813551) ||

3
src/intel/vulkan/genX_cmd_compute.c
View file

@ -852,7 +852,8 @@ genX(cmd_buffer_ray_query_globals)(struct anv_cmd_buffer *cmd_buffer)
.bo = device->ray_query_bo[idx],
.offset = (i + 1) * (device->ray_query_bo[idx]->size / 2),
},
.AsyncRTStackSize = BRW_RT_SIZEOF_RAY_QUERY / 64,
.AsyncRTStackSize =
cmd_buffer->state.rt.scratch.layout.ray_stack_stride / 64,
.NumDSSRTStacks = stack_ids_per_dss,
.MaxBVHLevels = BRW_RT_MAX_BVH_LEVELS,
.Flags = RT_DEPTH_TEST_LESS_EQUAL,