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anv: Add Tile Cache Flush for Unified Cache.

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This commit is contained in:
Rafael Antognolli 2019-04-30 13:34:20 -07:00
parent a99c67b690
commit 3c317e8187
3 changed files with 45 additions and 1 deletions
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4
src/intel/vulkan/anv_private.h
View file

@ -2046,6 +2046,7 @@ enum anv_pipe_bits {
ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT = (1 << 3),
ANV_PIPE_VF_CACHE_INVALIDATE_BIT = (1 << 4),
ANV_PIPE_DATA_CACHE_FLUSH_BIT = (1 << 5),
ANV_PIPE_TILE_CACHE_FLUSH_BIT = (1 << 6),
ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT = (1 << 10),
ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT = (1 << 11),
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT = (1 << 12),
@ -2071,7 +2072,8 @@ enum anv_pipe_bits {
#define ANV_PIPE_FLUSH_BITS ( \
ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | \
ANV_PIPE_TILE_CACHE_FLUSH_BIT)
#define ANV_PIPE_STALL_BITS ( \
ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \

6
src/intel/vulkan/gen8_cmd_buffer.c
View file

@ -140,6 +140,9 @@ genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer *cmd_buffer, bool enable)
pc.DepthCacheFlushEnable = true;
pc.CommandStreamerStallEnable = true;
pc.RenderTargetCacheFlushEnable = true;
#if GEN_GEN >= 12
pc.TileCacheFlushEnable = true;
#endif
}
#if GEN_GEN == 9
@ -179,6 +182,9 @@ genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer *cmd_buffer, bool enable)
pc.DepthStallEnable = true;
pc.DepthCacheFlushEnable = true;
pc.RenderTargetCacheFlushEnable = true;
#if GEN_GEN >= 12
pc.TileCacheFlushEnable = true;
#endif
}
}

36
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -70,6 +70,9 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
pc.DCFlushEnable = true;
pc.RenderTargetCacheFlushEnable = true;
pc.CommandStreamerStallEnable = true;
#if GEN_GEN >= 12
pc.TileCacheFlushEnable = true;
#endif
}
anv_batch_emit(&cmd_buffer->batch, GENX(STATE_BASE_ADDRESS), sba) {
@ -1805,8 +1808,29 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer)
bits &= ~ANV_PIPE_NEEDS_CS_STALL_BIT;
}
if (GEN_GEN >= 12 &&
((bits & ANV_PIPE_DEPTH_CACHE_FLUSH_BIT) ||
(bits & ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT))) {
/* From the PIPE_CONTROL instruction table, bit 28 (Tile Cache Flush
* Enable):
*
* Unified Cache (Tile Cache Disabled):
*
* When the Color and Depth (Z) streams are enabled to be cached in
* the DC space of L2, Software must use "Render Target Cache Flush
* Enable" and "Depth Cache Flush Enable" along with "Tile Cache
* Flush" for getting the color and depth (Z) write data to be
* globally observable. In this mode of operation it is not required
* to set "CS Stall" upon setting "Tile Cache Flush" bit.
*/
bits |= ANV_PIPE_TILE_CACHE_FLUSH_BIT;
}
if (bits & (ANV_PIPE_FLUSH_BITS | ANV_PIPE_CS_STALL_BIT)) {
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe) {
#if GEN_GEN >= 12
pipe.TileCacheFlushEnable = bits & ANV_PIPE_TILE_CACHE_FLUSH_BIT;
#endif
pipe.DepthCacheFlushEnable = bits & ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
pipe.DCFlushEnable = bits & ANV_PIPE_DATA_CACHE_FLUSH_BIT;
pipe.RenderTargetCacheFlushEnable =
@ -2364,6 +2388,9 @@ emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
pc.RenderTargetCacheFlushEnable = true;
pc.StallAtPixelScoreboard = true;
#if GEN_GEN >= 12
pc.TileCacheFlushEnable = true;
#endif
}
#endif
@ -3911,6 +3938,9 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
pc.DCFlushEnable = true;
pc.PostSyncOperation = NoWrite;
pc.CommandStreamerStallEnable = true;
#if GEN_GEN >= 12
pc.TileCacheFlushEnable = true;
#endif
}
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
@ -3919,6 +3949,9 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
pc.StateCacheInvalidationEnable = true;
pc.InstructionCacheInvalidateEnable = true;
pc.PostSyncOperation = NoWrite;
#if GEN_GEN >= 12
pc.TileCacheFlushEnable = true;
#endif
}
anv_batch_emit(&cmd_buffer->batch, GENX(PIPELINE_SELECT), ps) {
@ -3985,6 +4018,9 @@ genX(cmd_buffer_emit_gen7_depth_flush)(struct anv_cmd_buffer *cmd_buffer)
}
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe) {
pipe.DepthCacheFlushEnable = true;
#if GEN_GEN >= 12
pipe.TileCacheFlushEnable = true;
#endif
}
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe) {
pipe.DepthStallEnable = true;