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broadcom/vc5: Move stencil state packing to the CSO.

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Only the stencil ref comes in as dynamic state at emit time.
This commit is contained in:
Eric Anholt 2017-11-01 15:18:34 -07:00
parent 3da39f2297
commit 3be820477f
3 changed files with 47 additions and 27 deletions
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3
src/gallium/drivers/vc5/vc5_context.h
View file

@ -394,6 +394,9 @@ struct vc5_depth_stencil_alpha_state {
* Index 2 is the writemask config if it's not a common mask value.
*/
uint32_t stencil_uniforms[3];
uint8_t stencil_front[8];
uint8_t stencil_back[8];
};
#define perf_debug(...) do { \

36
src/gallium/drivers/vc5/vc5_emit.c
View file

@ -388,39 +388,21 @@ vc5_emit_state(struct pipe_context *pctx)
}
}
if (vc5->dirty & (VC5_DIRTY_ZSA | VC5_DIRTY_STENCIL_REF) &&
vc5->zsa->base.stencil[0].enabled) {
if (vc5->dirty & (VC5_DIRTY_ZSA | VC5_DIRTY_STENCIL_REF)) {
struct pipe_stencil_state *front = &vc5->zsa->base.stencil[0];
struct pipe_stencil_state *back = &vc5->zsa->base.stencil[1];
cl_emit(&job->bcl, STENCIL_CONFIG, config) {
config.front_config = true;
config.back_config = !back->enabled;
config.stencil_write_mask = front->writemask;
config.stencil_test_mask = front->valuemask;
config.stencil_test_function = front->func;
config.stencil_pass_op = front->zpass_op;
config.depth_test_fail_op = front->zfail_op;
config.stencil_test_fail_op = front->fail_op;
config.stencil_ref_value = vc5->stencil_ref.ref_value[0];
if (front->enabled) {
cl_emit_with_prepacked(&job->bcl, STENCIL_CONFIG,
vc5->zsa->stencil_front, config) {
config.stencil_ref_value =
vc5->stencil_ref.ref_value[1];
}
}
if (back->enabled) {
cl_emit(&job->bcl, STENCIL_CONFIG, config) {
config.front_config = false;
config.back_config = true;
config.stencil_write_mask = back->writemask;
config.stencil_test_mask = back->valuemask;
config.stencil_test_function = back->func;
config.stencil_pass_op = back->zpass_op;
config.depth_test_fail_op = back->zfail_op;
config.stencil_test_fail_op = back->fail_op;
cl_emit_with_prepacked(&job->bcl, STENCIL_CONFIG,
vc5->zsa->stencil_back, config) {
config.stencil_ref_value =
vc5->stencil_ref.ref_value[1];
}

35
src/gallium/drivers/vc5/vc5_state.c
View file

@ -153,6 +153,41 @@ vc5_create_depth_stencil_alpha_state(struct pipe_context *pctx,
cso->stencil[1].zfail_op == PIPE_STENCIL_OP_KEEP))));
}
const struct pipe_stencil_state *front = &cso->stencil[0];
const struct pipe_stencil_state *back = &cso->stencil[1];
if (front->enabled) {
v3dx_pack(&so->stencil_front, STENCIL_CONFIG, config) {
config.front_config = true;
/* If !back->enabled, then the front values should be
* used for both front and back-facing primitives.
*/
config.back_config = !back->enabled;
config.stencil_write_mask = front->writemask;
config.stencil_test_mask = front->valuemask;
config.stencil_test_function = front->func;
config.stencil_pass_op = front->zpass_op;
config.depth_test_fail_op = front->zfail_op;
config.stencil_test_fail_op = front->fail_op;
}
}
if (back->enabled) {
v3dx_pack(&so->stencil_back, STENCIL_CONFIG, config) {
config.front_config = false;
config.back_config = true;
config.stencil_write_mask = back->writemask;
config.stencil_test_mask = back->valuemask;
config.stencil_test_function = back->func;
config.stencil_pass_op = back->zpass_op;
config.depth_test_fail_op = back->zfail_op;
config.stencil_test_fail_op = back->fail_op;
}
}
return so;
}