From 3bdfe0e2a3d394dfda5c1445ff07f8b5bdb374f8 Mon Sep 17 00:00:00 2001
From: Nanley Chery <nanley.g.chery@intel.com>
Date: Thu, 28 Apr 2022 08:54:26 -0700
Subject: [PATCH] intel/isl: Update quote for XeHP's CCS halign rule

Clarify that the depth/stencil rules take precedence over the CCS rules.

From Bspec 43862 (r52666).

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29167>
---
 src/intel/isl/isl_gfx12.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/isl/isl_gfx12.c b/src/intel/isl/isl_gfx12.c
index b92dc6b79d5..98aa921b750 100644
--- a/src/intel/isl/isl_gfx12.c
+++ b/src/intel/isl/isl_gfx12.c
@@ -220,7 +220,7 @@ isl_gfx125_choose_image_alignment_el(const struct isl_device *dev,
       /* From RENDER_SURFACE_STATE::SurfaceHorizontalAlignment,
        *
        *    - Losslessly Compressed Surfaces Must be HALIGN=128 for all
-       *      supported Bpp
+       *      supported Bpp, if other restriction are not applied
        *    - Linear Surfaces surfaces must use HALIGN=128, including 1D which
        *      is always Linear.
        */