From 3b9a1ce4ca1bf0f143ede1c5a72f129ed956a358 Mon Sep 17 00:00:00 2001 From: Rhys Perry Date: Wed, 11 Jun 2025 10:32:06 +0100 Subject: [PATCH] aco: remove RegClass::as_subdword MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Rhys Perry Reviewed-by: Daniel Schürmann Part-of: --- src/amd/compiler/aco_ir.h | 3 +-- .../aco_isel_helpers.cpp | 24 ++++++------------- .../aco_select_nir_alu.cpp | 3 +-- 3 files changed, 9 insertions(+), 21 deletions(-) diff --git a/src/amd/compiler/aco_ir.h b/src/amd/compiler/aco_ir.h index 4b02737524f..b8601cbfebc 100644 --- a/src/amd/compiler/aco_ir.h +++ b/src/amd/compiler/aco_ir.h @@ -324,14 +324,13 @@ struct RegClass { constexpr unsigned size() const { return (bytes() + 3) >> 2; } constexpr bool is_linear() const { return rc <= RC::s16 || is_linear_vgpr(); } constexpr RegClass as_linear() const { return RegClass((RC)(rc | (1 << 6))); } - constexpr RegClass as_subdword() const { return RegClass((RC)(rc | 1 << 7)); } static constexpr RegClass get(RegType type, unsigned bytes) { if (type == RegType::sgpr) { return RegClass(type, DIV_ROUND_UP(bytes, 4u)); } else { - return bytes % 4u ? RegClass(type, bytes).as_subdword() : RegClass(type, bytes / 4u); + return bytes % 4u ? RegClass((RC)(1 << 5 | 1 << 7 | bytes)) : RegClass(type, bytes / 4u); } } diff --git a/src/amd/compiler/instruction_selection/aco_isel_helpers.cpp b/src/amd/compiler/instruction_selection/aco_isel_helpers.cpp index 05c9345f0a1..c753168e757 100644 --- a/src/amd/compiler/instruction_selection/aco_isel_helpers.cpp +++ b/src/amd/compiler/instruction_selection/aco_isel_helpers.cpp @@ -141,18 +141,12 @@ emit_split_vector(isel_context* ctx, Temp vec_src, unsigned num_components) return; if (ctx->allocated_vec.find(vec_src.id()) != ctx->allocated_vec.end()) return; - RegClass rc; - if (num_components > vec_src.size()) { - if (vec_src.type() == RegType::sgpr) { - /* should still help get_alu_src() */ - emit_split_vector(ctx, vec_src, vec_src.size()); - return; - } - /* sub-dword split */ - rc = RegClass(RegType::vgpr, vec_src.bytes() / num_components).as_subdword(); - } else { - rc = RegClass(vec_src.type(), vec_src.size() / num_components); + if (num_components > vec_src.size() && vec_src.type() == RegType::sgpr) { + /* sub-dword split: should still help get_alu_src() */ + emit_split_vector(ctx, vec_src, vec_src.size()); + return; } + RegClass rc = RegClass::get(vec_src.type(), vec_src.bytes() / num_components); aco_ptr split{ create_instruction(aco_opcode::p_split_vector, Format::PSEUDO, 1, num_components)}; split->operands[0] = Operand(vec_src); @@ -241,12 +235,8 @@ convert_int(isel_context* ctx, Builder& bld, Temp src, unsigned src_bits, unsign assert(!(sign_extend && dst_bits < src_bits) && "Shrinking integers is not supported for signed inputs"); - if (!dst.id()) { - if (dst_bits % 32 == 0 || src.type() == RegType::sgpr) - dst = bld.tmp(src.type(), DIV_ROUND_UP(dst_bits, 32u)); - else - dst = bld.tmp(RegClass(RegType::vgpr, dst_bits / 8u).as_subdword()); - } + if (!dst.id()) + dst = bld.tmp(RegClass::get(src.type(), dst_bits / 8u)); assert(src.type() == RegType::sgpr || src_bits == src.bytes() * 8); assert(dst.type() == RegType::sgpr || dst_bits == dst.bytes() * 8); diff --git a/src/amd/compiler/instruction_selection/aco_select_nir_alu.cpp b/src/amd/compiler/instruction_selection/aco_select_nir_alu.cpp index 46922ab55b1..17cc32cf1ab 100644 --- a/src/amd/compiler/instruction_selection/aco_select_nir_alu.cpp +++ b/src/amd/compiler/instruction_selection/aco_select_nir_alu.cpp @@ -88,8 +88,7 @@ get_alu_src(struct isel_context* ctx, nir_alu_src src, unsigned size = 1) if (as_uniform) vec = as_vgpr(ctx, vec); - RegClass elem_rc = elem_size < 4 ? RegClass(vec.type(), elem_size).as_subdword() - : RegClass(vec.type(), elem_size / 4); + RegClass elem_rc = RegClass::get(vec.type(), elem_size); if (size == 1) { return emit_extract_vector(ctx, vec, src.swizzle[0], elem_rc); } else {