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virgl: support PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT

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We should have GL4.5 with this.  Piglit tests should now pass.
In terms of performance, we're between 70% to 80% of host
performance on Iris, based on a apitrace of a 2013 GL4.5
game:

11.204 FPS (guest)
15.947 FPS (host)

This is still better than the status quo, when said game was unplayable
with Virgl due to an inefficient GL4.3 fallback.

TEST=piglit -t arb_buffer_storage all results/ passes

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4821>
This commit is contained in:
Gurchetan Singh 2020-04-28 17:26:18 -07:00
parent cd31f46f08
commit 3b54e5837a
3 changed files with 18 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
src/gallium/drivers/virgl/virgl_buffer.c
View file

@ -33,8 +33,10 @@ static void virgl_buffer_transfer_unmap(struct pipe_context *ctx,
{
struct virgl_context *vctx = virgl_context(ctx);
struct virgl_transfer *trans = virgl_transfer(transfer);
bool persistent_coherent = trans->base.usage & (PIPE_MAP_PERSISTENT |
PIPE_MAP_COHERENT);
if (trans->base.usage & PIPE_MAP_WRITE) {
if ((trans->base.usage & PIPE_MAP_WRITE) && !persistent_coherent) {
if (transfer->usage & PIPE_MAP_FLUSH_EXPLICIT) {
if (trans->range.end <= trans->range.start) {
virgl_resource_destroy_transfer(vctx, trans);

4
src/gallium/drivers/virgl/virgl_screen.c
View file

@ -291,6 +291,10 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
return !!(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_MULTI_DRAW_INDIRECT);
case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
return !!(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_INDIRECT_PARAMS);
case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
return (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_ARB_BUFFER_STORAGE) &&
(vscreen->caps.caps.v2.host_feature_check_version >= 4) &&
vscreen->vws->supports_coherent;
case PIPE_CAP_PCI_GROUP:
case PIPE_CAP_PCI_BUS:
case PIPE_CAP_PCI_DEVICE:

14
src/gallium/winsys/virgl/drm/virgl_drm_winsys.c
View file

@ -369,9 +369,17 @@ virgl_drm_winsys_resource_cache_create(struct virgl_winsys *qws,
mtx_unlock(&qdws->mutex);
alloc:
res = virgl_drm_winsys_resource_create(qws, target, format, bind,
width, height, depth, array_size,
last_level, nr_samples, size, false);
if (flags & (VIRGL_RESOURCE_FLAG_MAP_PERSISTENT |
VIRGL_RESOURCE_FLAG_MAP_COHERENT))
res = virgl_drm_winsys_resource_create_blob(qws, target, format, bind,
width, height, depth,
array_size, last_level,
nr_samples, flags, size);
else
res = virgl_drm_winsys_resource_create(qws, target, format, bind, width,
height, depth, array_size,
last_level, nr_samples, size,
false);
return res;
}