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i965/fs: Ensure delta_x/y are even-aligned registers on Gen6.

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The BSpec says this applies to Gen6 as well.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
This commit is contained in:
Matt Turner 2015-04-02 16:57:10 -07:00
parent 958b4965a2
commit 3b4abdae04
2 changed files with 3 additions and 3 deletions
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2
src/mesa/drivers/dri/i965/brw_fs_generator.cpp
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@ -428,7 +428,7 @@ fs_generator::generate_linterp(fs_inst *inst,
if (brw->has_pln &&
delta_y.nr == delta_x.nr + 1 &&
(brw->gen >= 6 || (delta_x.nr & 1) == 0)) {
(brw->gen >= 7 || (delta_x.nr & 1) == 0)) {
brw_PLN(p, dst, interp, delta_x);
} else {
brw_LINE(p, brw_null_reg(), interp, delta_x);

4
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
View file

@ -245,9 +245,9 @@ brw_alloc_reg_set(struct intel_screen *screen, int reg_width)
assert(reg == ra_reg_count);
/* Add a special class for aligned pairs, which we'll put delta_x/y
* in on gen5 so that we can do PLN.
* in on Gen <= 6 so that we can do PLN.
*/
if (devinfo->has_pln && reg_width == 1 && devinfo->gen < 6) {
if (devinfo->has_pln && reg_width == 1 && devinfo->gen <= 6) {
aligned_pairs_class = ra_alloc_reg_class(regs);
for (int i = 0; i < pairs_reg_count; i++) {