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i965: Cite the Ivybridge PRM for VS PIPE_CONTROL workarounds.

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Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Kenneth Graunke 2013-07-10 13:39:19 -07:00
parent 9a86875c6b
commit 3b3a440d2b
1 changed files with 2 additions and 2 deletions
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4
src/mesa/drivers/dri/i965/intel_batchbuffer.c
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@ -419,8 +419,8 @@ intel_emit_depth_stall_flushes(struct brw_context *brw)
}
/**
* From the BSpec, volume 2a.03: VS Stage Input / State:
* "[DevIVB] A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
* From the Ivybridge PRM, Volume 2 Part 1, Section 3.2 (VS Stage Input):
* "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
* stall needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
* 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
* 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL needs