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radeonsi: disable WGP mode on gfx10.3 to prevent hangs

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I think that reducing the CU mask to 1 disabled CU per SA broke the WGP mode
on VanGogh, causing a hang. To be sure, disable it on all chips.

Fixes: 9538b9a68e - radeonsi: add support for Sienna Cichlid

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7721>
(cherry picked from commit 69c927debe)
This commit is contained in:
Marek Olšák 2020-11-25 19:51:42 -05:00 • committed by Dylan Baker
parent cd94b261fc
commit 3b2f3e626f
2 changed files with 5 additions and 2 deletions
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2
.pick_status.json
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@ -904,7 +904,7 @@
"description": "radeonsi: disable WGP mode on gfx10.3 to prevent hangs",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"master_sha": null,
"because_sha": "9538b9a68ed9aa0f8a231d6bf681f6f0a2a9d341"
},

5
src/gallium/drivers/radeonsi/si_state_shaders.c
View file

@ -1128,7 +1128,10 @@ static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader
pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
S_00B228_VGPRS((shader->config.num_vgprs - 1) / (wave_size == 32 ? 8 : 4)) |
S_00B228_FLOAT_MODE(shader->config.float_mode) | S_00B228_DX10_CLAMP(1) |
S_00B228_MEM_ORDERED(1) | S_00B228_WGP_MODE(1) |
S_00B228_MEM_ORDERED(1) |
/* Disable the WGP mode on gfx10.3 because it can hang. (it happened on VanGogh)
* Let's disable it on all chips that disable exactly 1 CU per SA for GS. */
S_00B228_WGP_MODE(sscreen->info.chip_class == GFX10) |
S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |