fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-01-07 08:40:11 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

freedreno/registers: Cleanup bindless-base regs

Browse source 
Make it clear that the low two bits of the 64b address is it's own
bitfield.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20456>
This commit is contained in:
Rob Clark 2022-12-29 13:29:04 -08:00 • committed by Marge Bot
parent 3fa2ce0890
commit 3b2e1b2d32
4 changed files with 94 additions and 75 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

120
src/freedreno/.gitlab-ci/reference/crash.log
View file

@ -7008,19 +7008,19 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
- context: 0
00000140 HLSQ_FS_CNTL: { CONSTLEN = 256 | ENABLED }
00000000 HLSQ_SHARED_CONSTS: { 0 }
00000000 HLSQ_BINDLESS_BASE[0].ADDR: 0
00000000 HLSQ_BINDLESS_BASE[0x1].ADDR: 0
00000000 HLSQ_BINDLESS_BASE[0x2].ADDR: 0
00000000 HLSQ_BINDLESS_BASE[0x3].ADDR: 0
00000000 HLSQ_BINDLESS_BASE[0x4].ADDR: 0
00000000 HLSQ_BINDLESS_BASE[0].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0 }
00000000 HLSQ_BINDLESS_BASE[0x1].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0 }
00000000 HLSQ_BINDLESS_BASE[0x2].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0 }
00000000 HLSQ_BINDLESS_BASE[0x3].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0 }
00000000 HLSQ_BINDLESS_BASE[0x4].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0 }
- context: 1
00000140 HLSQ_FS_CNTL: { CONSTLEN = 256 | ENABLED }
00000000 HLSQ_SHARED_CONSTS: { 0 }
00000000 HLSQ_BINDLESS_BASE[0].ADDR: 0
00000000 HLSQ_BINDLESS_BASE[0x1].ADDR: 0
00000000 HLSQ_BINDLESS_BASE[0x2].ADDR: 0
00000000 HLSQ_BINDLESS_BASE[0x3].ADDR: 0
00000000 HLSQ_BINDLESS_BASE[0x4].ADDR: 0
00000000 HLSQ_BINDLESS_BASE[0].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0 }
00000000 HLSQ_BINDLESS_BASE[0x1].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0 }
00000000 HLSQ_BINDLESS_BASE[0x2].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0 }
00000000 HLSQ_BINDLESS_BASE[0x3].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0 }
00000000 HLSQ_BINDLESS_BASE[0x4].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0 }
- cluster-name: CLUSTER_SP_VS
- context: 0
deadbeef HLSQ_2D_EVENT_CMD: { STATE_ID = 0xbe | EVENT = 0x6f | 0xdead0080 }
@ -7031,22 +7031,22 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_MODE_CONTROL: { ISAMMODE = 0 }
00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000000 SP_FS_INSTRLEN: 0
cd302764a40a SP_BINDLESS_BASE[0].ADDR: 0xcd302764a40a
17dc493870830 SP_BINDLESS_BASE[0x1].ADDR: 0x17dc493870830
14b45d3064206 SP_BINDLESS_BASE[0x2].ADDR: 0x14b45d3064206
1ddc9bfafe9ba SP_BINDLESS_BASE[0x3].ADDR: 0x1ddc9bfafe9ba
bd3befda4292 SP_BINDLESS_BASE[0x4].ADDR: 0xbd3befda4292
cd302764a40a SP_BINDLESS_BASE[0].DESCRIPTOR: { DESC_SIZE = 0x2 | ADDR = 0xcd302764a408 }
17dc493870830 SP_BINDLESS_BASE[0x1].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0x17dc493870830 }
14b45d3064206 SP_BINDLESS_BASE[0x2].DESCRIPTOR: { DESC_SIZE = 0x2 | ADDR = 0x14b45d3064204 }
1ddc9bfafe9ba SP_BINDLESS_BASE[0x3].DESCRIPTOR: { DESC_SIZE = 0x2 | ADDR = 0x1ddc9bfafe9b8 }
bd3befda4292 SP_BINDLESS_BASE[0x4].DESCRIPTOR: { DESC_SIZE = 0x2 | ADDR = 0xbd3befda4290 }
13c400c0e0691 SP_IBO: 0x13c400c0e0691
00000040 SP_IBO_COUNT: 64
- context: 1
00000000 SP_MODE_CONTROL: { ISAMMODE = 0 }
00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000000 SP_FS_INSTRLEN: 0
cd302764a40a SP_BINDLESS_BASE[0].ADDR: 0xcd302764a40a
17dc493870830 SP_BINDLESS_BASE[0x1].ADDR: 0x17dc493870830
14b45d3064206 SP_BINDLESS_BASE[0x2].ADDR: 0x14b45d3064206
1ddc9bfafe9ba SP_BINDLESS_BASE[0x3].ADDR: 0x1ddc9bfafe9ba
bd3befda4292 SP_BINDLESS_BASE[0x4].ADDR: 0xbd3befda4292
cd302764a40a SP_BINDLESS_BASE[0].DESCRIPTOR: { DESC_SIZE = 0x2 | ADDR = 0xcd302764a408 }
17dc493870830 SP_BINDLESS_BASE[0x1].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0x17dc493870830 }
14b45d3064206 SP_BINDLESS_BASE[0x2].DESCRIPTOR: { DESC_SIZE = 0x2 | ADDR = 0x14b45d3064204 }
1ddc9bfafe9ba SP_BINDLESS_BASE[0x3].DESCRIPTOR: { DESC_SIZE = 0x2 | ADDR = 0x1ddc9bfafe9b8 }
bd3befda4292 SP_BINDLESS_BASE[0x4].DESCRIPTOR: { DESC_SIZE = 0x2 | ADDR = 0xbd3befda4290 }
13c400c0e0691 SP_IBO: 0x13c400c0e0691
00000040 SP_IBO_COUNT: 64
- cluster-name: CLUSTER_SP_VS
@ -7097,11 +7097,11 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000001 HLSQ_CS_KERNEL_GROUP_Z: 0x1
40304000 HLSQ_LOAD_STATE_FRAG_CMD: 0x40304000
8c415430 HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR: 0x8c415430
00000000 HLSQ_CS_BINDLESS_BASE[0].ADDR: 0
00000000 HLSQ_CS_BINDLESS_BASE[0x1].ADDR: 0
00000000 HLSQ_CS_BINDLESS_BASE[0x2].ADDR: 0
00000000 HLSQ_CS_BINDLESS_BASE[0x3].ADDR: 0
00000000 HLSQ_CS_BINDLESS_BASE[0x4].ADDR: 0
00000000 HLSQ_CS_BINDLESS_BASE[0].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0 }
00000000 HLSQ_CS_BINDLESS_BASE[0x1].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0 }
00000000 HLSQ_CS_BINDLESS_BASE[0x2].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0 }
00000000 HLSQ_CS_BINDLESS_BASE[0x3].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0 }
00000000 HLSQ_CS_BINDLESS_BASE[0x4].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0 }
- context: 1
00000001 HLSQ_FS_CNTL_0: { THREADSIZE = THREAD128 }
00000007 HLSQ_CONTROL_1_REG: 0x7
@ -7124,11 +7124,11 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000001 HLSQ_CS_KERNEL_GROUP_Z: 0x1
40304000 HLSQ_LOAD_STATE_FRAG_CMD: 0x40304000
8c415430 HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR: 0x8c415430
00000000 HLSQ_CS_BINDLESS_BASE[0].ADDR: 0
00000000 HLSQ_CS_BINDLESS_BASE[0x1].ADDR: 0
00000000 HLSQ_CS_BINDLESS_BASE[0x2].ADDR: 0
00000000 HLSQ_CS_BINDLESS_BASE[0x3].ADDR: 0
00000000 HLSQ_CS_BINDLESS_BASE[0x4].ADDR: 0
00000000 HLSQ_CS_BINDLESS_BASE[0].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0 }
00000000 HLSQ_CS_BINDLESS_BASE[0x1].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0 }
00000000 HLSQ_CS_BINDLESS_BASE[0x2].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0 }
00000000 HLSQ_CS_BINDLESS_BASE[0x3].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0 }
00000000 HLSQ_CS_BINDLESS_BASE[0x4].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0 }
- cluster-name: CLUSTER_SP_PS
- context: 0
deadbeef HLSQ_2D_EVENT_CMD: { STATE_ID = 0xbe | EVENT = 0x6f | 0xdead0080 }
@ -7194,11 +7194,11 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
1ef50bf8b2a24 SP_CS_TEX_SAMP: 0x1ef50bf8b2a24
1998693f2108 SP_FS_TEX_CONST: 0x1998693f2108
1b500be19e77a SP_CS_TEX_CONST: 0x1b500be19e77a
121917dd2a41c SP_CS_BINDLESS_BASE[0].ADDR: 0x121917dd2a41c
f4087d568030 SP_CS_BINDLESS_BASE[0x1].ADDR: 0xf4087d568030
76cd6915b33d SP_CS_BINDLESS_BASE[0x2].ADDR: 0x76cd6915b33d
1f2333cfd0197 SP_CS_BINDLESS_BASE[0x3].ADDR: 0x1f2333cfd0197
16204a6b745da SP_CS_BINDLESS_BASE[0x4].ADDR: 0x16204a6b745da
121917dd2a41c SP_CS_BINDLESS_BASE[0].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0x121917dd2a41c }
f4087d568030 SP_CS_BINDLESS_BASE[0x1].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0xf4087d568030 }
76cd6915b33d SP_CS_BINDLESS_BASE[0x2].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_16B | ADDR = 0x76cd6915b33c }
1f2333cfd0197 SP_CS_BINDLESS_BASE[0x3].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_64B | ADDR = 0x1f2333cfd0194 }
16204a6b745da SP_CS_BINDLESS_BASE[0x4].DESCRIPTOR: { DESC_SIZE = 0x2 | ADDR = 0x16204a6b745d8 }
1d693fdfdd365 SP_CS_IBO: 0x1d693fdfdd365
00000040 SP_CS_IBO_COUNT: 64
00000000 0xaa30: 00000000
@ -7262,11 +7262,11 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
1ef50bf8b2a24 SP_CS_TEX_SAMP: 0x1ef50bf8b2a24
1998693f2108 SP_FS_TEX_CONST: 0x1998693f2108
1b500be19e77a SP_CS_TEX_CONST: 0x1b500be19e77a
121917dd2a41c SP_CS_BINDLESS_BASE[0].ADDR: 0x121917dd2a41c
f4087d568030 SP_CS_BINDLESS_BASE[0x1].ADDR: 0xf4087d568030
76cd6915b33d SP_CS_BINDLESS_BASE[0x2].ADDR: 0x76cd6915b33d
1f2333cfd0197 SP_CS_BINDLESS_BASE[0x3].ADDR: 0x1f2333cfd0197
16204a6b745da SP_CS_BINDLESS_BASE[0x4].ADDR: 0x16204a6b745da
121917dd2a41c SP_CS_BINDLESS_BASE[0].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0x121917dd2a41c }
f4087d568030 SP_CS_BINDLESS_BASE[0x1].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0xf4087d568030 }
76cd6915b33d SP_CS_BINDLESS_BASE[0x2].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_16B | ADDR = 0x76cd6915b33c }
1f2333cfd0197 SP_CS_BINDLESS_BASE[0x3].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_64B | ADDR = 0x1f2333cfd0194 }
16204a6b745da SP_CS_BINDLESS_BASE[0x4].DESCRIPTOR: { DESC_SIZE = 0x2 | ADDR = 0x16204a6b745d8 }
1d693fdfdd365 SP_CS_IBO: 0x1d693fdfdd365
00000040 SP_CS_IBO_COUNT: 64
00000000 0xaa30: 00000000
@ -7324,40 +7324,40 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
- context: 0
00000140 HLSQ_FS_CNTL: { CONSTLEN = 256 | ENABLED }
00000000 HLSQ_SHARED_CONSTS: { 0 }
00000000 HLSQ_BINDLESS_BASE[0].ADDR: 0
00000000 HLSQ_BINDLESS_BASE[0x1].ADDR: 0
00000000 HLSQ_BINDLESS_BASE[0x2].ADDR: 0
00000000 HLSQ_BINDLESS_BASE[0x3].ADDR: 0
00000000 HLSQ_BINDLESS_BASE[0x4].ADDR: 0
00000000 HLSQ_BINDLESS_BASE[0].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0 }
00000000 HLSQ_BINDLESS_BASE[0x1].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0 }
00000000 HLSQ_BINDLESS_BASE[0x2].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0 }
00000000 HLSQ_BINDLESS_BASE[0x3].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0 }
00000000 HLSQ_BINDLESS_BASE[0x4].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0 }
- context: 1
00000140 HLSQ_FS_CNTL: { CONSTLEN = 256 | ENABLED }
00000000 HLSQ_SHARED_CONSTS: { 0 }
00000000 HLSQ_BINDLESS_BASE[0].ADDR: 0
00000000 HLSQ_BINDLESS_BASE[0x1].ADDR: 0
00000000 HLSQ_BINDLESS_BASE[0x2].ADDR: 0
00000000 HLSQ_BINDLESS_BASE[0x3].ADDR: 0
00000000 HLSQ_BINDLESS_BASE[0x4].ADDR: 0
00000000 HLSQ_BINDLESS_BASE[0].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0 }
00000000 HLSQ_BINDLESS_BASE[0x1].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0 }
00000000 HLSQ_BINDLESS_BASE[0x2].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0 }
00000000 HLSQ_BINDLESS_BASE[0x3].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0 }
00000000 HLSQ_BINDLESS_BASE[0x4].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0 }
- cluster-name: CLUSTER_SP_PS
- context: 0
00000000 SP_MODE_CONTROL: { ISAMMODE = 0 }
00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000000 SP_FS_INSTRLEN: 0
7b4cdb94116 SP_BINDLESS_BASE[0].ADDR: 0x7b4cdb94116
1f54b6e5e07c3 SP_BINDLESS_BASE[0x1].ADDR: 0x1f54b6e5e07c3
1b4555f979543 SP_BINDLESS_BASE[0x2].ADDR: 0x1b4555f979543
13f8ca4d3a8cc SP_BINDLESS_BASE[0x3].ADDR: 0x13f8ca4d3a8cc
1ff601d337e76 SP_BINDLESS_BASE[0x4].ADDR: 0x1ff601d337e76
7b4cdb94116 SP_BINDLESS_BASE[0].DESCRIPTOR: { DESC_SIZE = 0x2 | ADDR = 0x7b4cdb94114 }
1f54b6e5e07c3 SP_BINDLESS_BASE[0x1].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_64B | ADDR = 0x1f54b6e5e07c0 }
1b4555f979543 SP_BINDLESS_BASE[0x2].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_64B | ADDR = 0x1b4555f979540 }
13f8ca4d3a8cc SP_BINDLESS_BASE[0x3].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0x13f8ca4d3a8cc }
1ff601d337e76 SP_BINDLESS_BASE[0x4].DESCRIPTOR: { DESC_SIZE = 0x2 | ADDR = 0x1ff601d337e74 }
10202e0e8bc18 SP_IBO: 0x10202e0e8bc18
00000040 SP_IBO_COUNT: 64
- context: 1
00000000 SP_MODE_CONTROL: { ISAMMODE = 0 }
00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000000 SP_FS_INSTRLEN: 0
7b4cdb94116 SP_BINDLESS_BASE[0].ADDR: 0x7b4cdb94116
1f54b6e5e07c3 SP_BINDLESS_BASE[0x1].ADDR: 0x1f54b6e5e07c3
1b4555f979543 SP_BINDLESS_BASE[0x2].ADDR: 0x1b4555f979543
13f8ca4d3a8cc SP_BINDLESS_BASE[0x3].ADDR: 0x13f8ca4d3a8cc
1ff601d337e76 SP_BINDLESS_BASE[0x4].ADDR: 0x1ff601d337e76
7b4cdb94116 SP_BINDLESS_BASE[0].DESCRIPTOR: { DESC_SIZE = 0x2 | ADDR = 0x7b4cdb94114 }
1f54b6e5e07c3 SP_BINDLESS_BASE[0x1].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_64B | ADDR = 0x1f54b6e5e07c0 }
1b4555f979543 SP_BINDLESS_BASE[0x2].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_64B | ADDR = 0x1b4555f979540 }
13f8ca4d3a8cc SP_BINDLESS_BASE[0x3].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0x13f8ca4d3a8cc }
1ff601d337e76 SP_BINDLESS_BASE[0x4].DESCRIPTOR: { DESC_SIZE = 0x2 | ADDR = 0x1ff601d337e74 }
10202e0e8bc18 SP_IBO: 0x10202e0e8bc18
00000040 SP_IBO_COUNT: 64
- cluster-name: CLUSTER_SP_PS

4
src/freedreno/decode/cffdec.c
View file

@ -1513,8 +1513,8 @@ cp_load_state(uint32_t *dwords, uint32_t sizedwords, int level)
break;
case STATE_SRC_BINDLESS: {
const unsigned base_reg = stage == MESA_SHADER_COMPUTE
? regbase("HLSQ_CS_BINDLESS_BASE[0].ADDR")
: regbase("HLSQ_BINDLESS_BASE[0].ADDR");
? regbase("HLSQ_CS_BINDLESS_BASE[0].DESCRIPTOR")
: regbase("HLSQ_BINDLESS_BASE[0].DESCRIPTOR");
if (is_64b()) {
const unsigned reg = base_reg + (dwords[1] >> 28) * 2;

35
src/freedreno/registers/adreno/a6xx.xml
View file

@ -3340,9 +3340,20 @@ to upconvert to 32b float internally?
<reg64 offset="0xa9e4" name="SP_FS_TEX_CONST" type="address" align="64"/>
<reg64 offset="0xa9e6" name="SP_CS_TEX_CONST" type="address" align="64"/>
<enum name="a6xx_bindless_descriptor_size">
<doc>
This can alternatively be interpreted as a pitch shift, ie, the
descriptor size is 2 &lt;&lt; N dwords
</doc>
<value value="1" name="BINDLESS_DESCRIPTOR_16B"/>
<value value="3" name="BINDLESS_DESCRIPTOR_64B"/>
</enum>
<array offset="0xa9e8" name="SP_CS_BINDLESS_BASE" stride="2" length="5">
<!-- TODO: probably align=64 with 6 flags bits in the low bits ? -->
<reg64 offset="0" name="ADDR" type="address"/>
<reg64 offset="0" name="DESCRIPTOR">
<bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>
<bitfield name="ADDR" low="2" high="63" shr="2" type="address"/>
</reg64>
</array>
<!--
@ -3379,8 +3390,10 @@ to upconvert to 32b float internally?
<reg32 offset="0xab05" name="SP_FS_INSTRLEN" low="0" high="27" type="uint"/>
<array offset="0xab10" name="SP_BINDLESS_BASE" stride="2" length="5">
<!-- TODO: probably align=64 with 6 flags bits in the low bits? -->
<reg64 offset="0" name="ADDR" type="address"/>
<reg64 offset="0" name="DESCRIPTOR">
<bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>
<bitfield name="ADDR" low="2" high="63" shr="2" type="address"/>
</reg64>
</array>
<!--
@ -3623,8 +3636,10 @@ to upconvert to 32b float internally?
<!-- mirror of SP_CS_BINDLESS_BASE -->
<array offset="0xb9c0" name="HLSQ_CS_BINDLESS_BASE" stride="2" length="5">
<!-- 64 alignment, 2 low bits for unknown flags (always 0x3 when enabled?) -->
<reg64 offset="0" name="ADDR" type="waddress"/>
<reg64 offset="0" name="DESCRIPTOR">
<bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>
<bitfield name="ADDR" low="2" high="63" shr="2" type="address"/>
</reg64>
</array>
<!-- new in a6xx gen4, mirror of SP_CS_UNKNOWN_A9B1? -->
@ -3702,8 +3717,10 @@ to upconvert to 32b float internally?
<!-- mirror of SP_BINDLESS_BASE -->
<array offset="0xbb20" name="HLSQ_BINDLESS_BASE" stride="2" length="5">
<!-- align 64 with two LSB for unknown flags (always 0x3 enabled) -->
<reg64 offset="0" name="ADDR" type="address"/>
<reg64 offset="0" name="DESCRIPTOR">
<bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>
<bitfield name="ADDR" low="2" high="63" shr="2" type="address"/>
</reg64>
</array>
<reg32 offset="0xbd80" name="HLSQ_2D_EVENT_CMD">
@ -3859,7 +3876,7 @@ to upconvert to 32b float internally?
<bitfield name="STRUCTSIZETEXELS" low="4" high="15" type="uint"/>
<bitfield name="STARTOFFSETTEXELS" low="16" high="21" type="uint"/>
<!-- minimum pitch (for mipmap levels): log2(pitchalign / 64) -->
<!-- minimum pitch (for mipmap levels): log2(pitchalign / 64) -->
<bitfield name="PITCHALIGN" low="0" high="3" type="uint"/>
<doc>Pitch in bytes (so actually stride)</doc>
<bitfield name="PITCH" low="7" high="28" type="uint"/>

10
src/freedreno/vulkan/tu_cmd_buffer.c
View file

@ -2164,7 +2164,7 @@ tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer,
TU_FROM_HANDLE(tu_descriptor_set, set, pDescriptorSets[i]);
descriptors_state->sets[idx] = set;
descriptors_state->set_iova[idx] = set->va | 3;
descriptors_state->set_iova[idx] = set->va | BINDLESS_DESCRIPTOR_64B;
if (!set)
continue;
@ -2249,7 +2249,7 @@ tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer,
memcpy(dynamic_desc_set.map, descriptors_state->dynamic_descriptors,
layout->dynamic_offset_size);
descriptors_state->set_iova[MAX_SETS] = dynamic_desc_set.iova | 3;
descriptors_state->set_iova[MAX_SETS] = dynamic_desc_set.iova | BINDLESS_DESCRIPTOR_64B;
descriptors_state->dynamic_bound = true;
}
@ -2292,7 +2292,8 @@ tu_CmdSetDescriptorBufferOffsetsEXT(
struct tu_descriptor_set_layout *set_layout = layout->set[idx].layout;
descriptors_state->set_iova[idx] =
(cmd->state.descriptor_buffer_iova[pBufferIndices[i]] + pOffsets[i]) | 3;
(cmd->state.descriptor_buffer_iova[pBufferIndices[i]] + pOffsets[i]) |
BINDLESS_DESCRIPTOR_64B;
if (set_layout->has_inline_uniforms)
cmd->state.dirty |= TU_CMD_DIRTY_SHADER_CONSTS;
@ -2319,7 +2320,8 @@ tu_CmdBindDescriptorBufferEmbeddedSamplersEXT(
descriptors_state->max_sets_bound =
MAX2(descriptors_state->max_sets_bound, set + 1);
descriptors_state->set_iova[set] = set_layout->embedded_samplers->iova | 3;
descriptors_state->set_iova[set] = set_layout->embedded_samplers->iova |
BINDLESS_DESCRIPTOR_64B;
tu_dirty_desc_sets(cmd, pipelineBindPoint);
}