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ir3/a7xx: Add new lock/unlock CS instructions

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Seen at the end of every compuite shader:

 %shader_assmebly%
 lock
 unlock
 end

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21498>
This commit is contained in:
Danylo Piliaiev 2023-02-16 20:34:33 +01:00 • committed by Marge Bot
parent 52ee3943eb
commit 3b0daf29e5
6 changed files with 38 additions and 0 deletions
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2
src/freedreno/ir3/disasm-a3xx.c
View file

@ -403,6 +403,8 @@ static const struct opc_info {
OPC(7, OPC_BAR, bar),
OPC(7, OPC_FENCE, fence),
OPC(7, OPC_LOCK, lock),
OPC(7, OPC_UNLOCK, unlock),
/* clang-format on */
#undef OPC
};

3
src/freedreno/ir3/instr-a3xx.h
View file

@ -367,6 +367,9 @@ typedef enum {
OPC_DCINV = _OPC(7, 5),
OPC_DCFLU = _OPC(7, 6),
OPC_LOCK = _OPC(7, 7),
OPC_UNLOCK = _OPC(7, 8),
/* meta instructions (category 8): */
#define OPC_META 8
/* placeholder instr to mark shader inputs: */

2
src/freedreno/ir3/ir3_lexer.l
View file

@ -387,6 +387,8 @@ static int parse_reg(const char *str)
"dccln.all" return TOKEN(T_OP_DCCLN);
"dcinv.all" return TOKEN(T_OP_DCINV);
"dcflu.all" return TOKEN(T_OP_DCFLU);
"lock" return TOKEN(T_OP_LOCK);
"unlock" return TOKEN(T_OP_UNLOCK);
"f16" return TOKEN(T_TYPE_F16);
"f32" return TOKEN(T_TYPE_F32);

4
src/freedreno/ir3/ir3_parser.y
View file

@ -626,6 +626,8 @@ static void print_token(FILE *file, int type, YYSTYPE value)
%token <tok> T_OP_DCCLN
%token <tok> T_OP_DCINV
%token <tok> T_OP_DCFLU
%token <tok> T_OP_LOCK
%token <tok> T_OP_UNLOCK
%token <u64> T_RAW
@ -1298,6 +1300,8 @@ cat7_instr: cat7_barrier
| cat7_data_cache
| T_OP_SLEEP { new_instr(OPC_SLEEP); }
| T_OP_ICINV { new_instr(OPC_ICINV); }
| T_OP_LOCK { new_instr(OPC_LOCK); }
| T_OP_UNLOCK { new_instr(OPC_UNLOCK); }
raw_instr: T_RAW {new_instr(OPC_META_RAW)->raw.value = $1;}

3
src/freedreno/ir3/tests/disasm.c
View file

@ -47,6 +47,7 @@
#define INSTR_4XX(i, d, ...) { .gpu_id = 420, .instr = #i, .expected = d, __VA_ARGS__ }
#define INSTR_5XX(i, d, ...) { .gpu_id = 540, .instr = #i, .expected = d, __VA_ARGS__ }
#define INSTR_6XX(i, d, ...) { .gpu_id = 630, .instr = #i, .expected = d, __VA_ARGS__ }
#define INSTR_7XX(i, d, ...) { .gpu_id = 730, .instr = #i, .expected = d, __VA_ARGS__ }
/* clang-format on */
static const struct test {
@ -421,6 +422,8 @@ static const struct test {
INSTR_6XX(e1080000_00000000, "sleep.l"),
INSTR_6XX(e2080000_00000000, "dccln.all"),
INSTR_7XX(e3c20000_00000000, "lock"),
INSTR_6XX(ffffffff_ffffffff, "raw 0xFFFFFFFFFFFFFFFF"),
/* clang-format on */
};

24
src/freedreno/isa/ir3-cat7.xml
View file

@ -145,4 +145,28 @@ SOFTWARE.
<pattern low="55" high="58">0110</pattern>
</bitset>
<bitset name="lock" extends="#instruction-cat7">
<doc>
Are met at the end of compute shader:
(sy)(jp)lock;
unlock;
end ;
</doc>
<gen min="700"/>
<display>
{SY}{JP}{NAME}
</display>
<pattern low="45" high="54">1000010000</pattern>
<pattern low="55" high="58">0111</pattern>
</bitset>
<bitset name="unlock" extends="#instruction-cat7">
<gen min="700"/>
<display>
{SY}{JP}{NAME}
</display>
<pattern low="45" high="54">1001010000</pattern>
<pattern low="55" high="58">0111</pattern>
</bitset>
</isa>