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i965: Disable 3DSTATE_WM_HZ_OP fields.

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Eric believes this to be wrong and unnecessary, as the command is
supposed to emit an implicit rectangle primitive.  However, empirically
the pixel pipeline is completely unreliable without it.  So for now, it
stays until someone comes up with a better solution.

We'll need to do better than this when we implement multisampling, HiZ,
or fast clears...but for now, this will do.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Kenneth Graunke 2013-12-06 03:07:54 -08:00
parent 4c4e0ed64b
commit 3ade766684
2 changed files with 10 additions and 0 deletions
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2
src/mesa/drivers/dri/i965/brw_defines.h
View file

@ -1752,6 +1752,8 @@ enum brw_message_target {
#define GEN8_BLEND_PRE_BLEND_COLOR_CLAMP_ENABLE (1 << 1)
#define GEN8_BLEND_POST_BLEND_COLOR_CLAMP_ENABLE (1 << 0)
#define _3DSTATE_WM_HZ_OP 0x7852 /* GEN8+ */
#define _3DSTATE_PS_BLEND 0x784D /* GEN8+ */
/* DW1 */
# define GEN8_PS_BLEND_ALPHA_TO_COVERAGE_ENABLE (1 << 31)

8
src/mesa/drivers/dri/i965/gen8_disable.c
View file

@ -29,6 +29,14 @@
static void
disable_stages(struct brw_context *brw)
{
BEGIN_BATCH(5);
OUT_BATCH(_3DSTATE_WM_HZ_OP << 16 | (5 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
ADVANCE_BATCH();
/* Disable the HS Unit */
BEGIN_BATCH(11);
OUT_BATCH(_3DSTATE_CONSTANT_HS << 16 | (11 - 2));