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r600g: fix evergreen new path

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glxgears seems to work, had somelockup but now they seems to have vanish.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
This commit is contained in:
Jerome Glisse 2010-09-24 16:17:28 -04:00
parent 49111213e4
commit 3ad4486bfe
3 changed files with 16 additions and 11 deletions
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2
src/gallium/drivers/r600/eg_hw_states.c
View file

@ -432,7 +432,7 @@ static void eg_dsa(struct r600_context *rctx, struct radeon_state *rstate)
if (query_running) {
db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
db_render_control |= S_028000_PERFECT_ZPASS_COUNTS(1);
// db_render_control |= S_028000_PERFECT_ZPASS_COUNTS(1);
}
rstate->states[EG_DSA__DB_STENCIL_CLEAR] = 0x00000000;

12
src/gallium/drivers/r600/evergreen_state.c
View file

@ -818,12 +818,11 @@ static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state
state->zsbuf->offset >> 8, 0xFFFFFFFF, rbuffer->bo);
r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028050_DB_Z_WRITE_BASE,
state->zsbuf->offset >> 8, 0xFFFFFFFF, rbuffer->bo);
r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028014_DB_HTILE_DATA_BASE,
state->zsbuf->offset >> 8, 0xFFFFFFFF, rbuffer->bo);
// r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028014_DB_HTILE_DATA_BASE, state->zsbuf->offset >> 8, 0xFFFFFFFF, rbuffer->bo);
r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028008_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028040_DB_Z_INFO,
S_028040_ARRAY_MODE(rtex->array_mode) | S_028040_FORMAT(format),
0xFFFFFFFF, NULL);
0xFFFFFFFF, rbuffer->bo);
r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028058_DB_DEPTH_SIZE,
S_028058_PITCH_TILE_MAX(pitch),
0xFFFFFFFF, NULL);
@ -1252,9 +1251,9 @@ void evergreen_init_config2(struct r600_pipe_context *rctx)
r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONFIG, R_009100_SPI_CONFIG_CNTL, 0x0, 0xFFFFFFFF, NULL);
r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONFIG, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL);
r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028350_SX_MISC, 0x0, 0xFFFFFFFF, NULL);
// r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028350_SX_MISC, 0x0, 0xFFFFFFFF, NULL);
r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONFIG, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, 0xFFFFFFFF, NULL);
// r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONFIG, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, 0xFFFFFFFF, NULL);
r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028A48_PA_SC_MODE_CNTL_0, 0x0, 0xFFFFFFFF, NULL);
r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_CONTEXT, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL);
@ -1424,8 +1423,7 @@ void evergreen_draw(struct pipe_context *ctx, const struct pipe_draw_info *info)
r600_pipe_state_add_reg(&vgt, EVERGREEN_GROUP_CONFIG, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL);
r600_pipe_state_add_reg(&vgt, EVERGREEN_GROUP_CONTEXT, R_028408_VGT_INDX_OFFSET, draw.start, 0xFFFFFFFF, NULL);
r600_pipe_state_add_reg(&vgt, EVERGREEN_GROUP_CONTEXT, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL);
// r600_pipe_state_add_reg(&vgt, EVERGREEN_GROUP_CONTEXT, R_028400_VGT_MAX_VTX_INDX, info->max_index, 0xFFFFFFFF, NULL);
r600_pipe_state_add_reg(&vgt, EVERGREEN_GROUP_CONTEXT, R_028400_VGT_MAX_VTX_INDX, 0x0000FFFF, 0xFFFFFFFF, NULL);
r600_pipe_state_add_reg(&vgt, EVERGREEN_GROUP_CONTEXT, R_028400_VGT_MAX_VTX_INDX, info->max_index, 0xFFFFFFFF, NULL);
r600_pipe_state_add_reg(&vgt, EVERGREEN_GROUP_CONTEXT, R_028404_VGT_MIN_VTX_INDX, 0x00000000, 0xFFFFFFFF, NULL);
r600_context_pipe_state_set(&rctx->ctx, &vgt);

13
src/gallium/winsys/r600/drm/evergreen_state.c
View file

@ -85,12 +85,19 @@ static const struct r600_reg evergreen_reg_list[] = {
{0, 0, R_02802C_DB_DEPTH_CLEAR},
{0, 0, R_028030_PA_SC_SCREEN_SCISSOR_TL},
{0, 0, R_028034_PA_SC_SCREEN_SCISSOR_BR},
{0, 0, GROUP_FORCE_NEW_BLOCK},
{1, 0, R_028040_DB_Z_INFO},
{0, 0, GROUP_FORCE_NEW_BLOCK},
{0, 0, R_028044_DB_STENCIL_INFO},
{0, 0, GROUP_FORCE_NEW_BLOCK},
{1, 0, R_028048_DB_Z_READ_BASE},
{0, 0, GROUP_FORCE_NEW_BLOCK},
{1, 0, R_02804C_DB_STENCIL_READ_BASE},
{0, 0, GROUP_FORCE_NEW_BLOCK},
{1, 0, R_028050_DB_Z_WRITE_BASE},
{0, 0, GROUP_FORCE_NEW_BLOCK},
{1, 0, R_028054_DB_STENCIL_WRITE_BASE},
{0, 0, GROUP_FORCE_NEW_BLOCK},
{0, 0, R_028058_DB_DEPTH_SIZE},
{0, 0, R_02805C_DB_DEPTH_SLICE},
{0, 0, R_028140_ALU_CONST_BUFFER_SIZE_PS_0},
@ -261,14 +268,14 @@ static const struct r600_reg evergreen_reg_list[] = {
{0, 0, R_02881C_PA_CL_VS_OUT_CNTL},
{0, 0, R_028820_PA_CL_NANINF_CNTL},
{0, 0, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1},
{1, 0, R_028840_SQ_PGM_START_PS},
{1, S_0085F0_SH_ACTION_ENA(1), R_028840_SQ_PGM_START_PS},
{0, 0, R_028844_SQ_PGM_RESOURCES_PS},
{0, 0, R_028848_SQ_PGM_RESOURCES_2_PS},
{0, 0, R_02884C_SQ_PGM_EXPORTS_PS},
{1, 0, R_02885C_SQ_PGM_START_VS},
{1, S_0085F0_SH_ACTION_ENA(1), R_02885C_SQ_PGM_START_VS},
{0, 0, R_028860_SQ_PGM_RESOURCES_VS},
{0, 0, R_028864_SQ_PGM_RESOURCES_2_VS},
{1, 0, R_0288A4_SQ_PGM_START_FS},
{1, S_0085F0_SH_ACTION_ENA(1), R_0288A4_SQ_PGM_START_FS},
{0, 0, R_0288A8_SQ_PGM_RESOURCES_FS},
{0, 0, R_0288EC_SQ_LDS_ALLOC_PS},
{0, 0, R_028900_SQ_ESGS_RING_ITEMSIZE},