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radeonsi: vectorize loads/store after ABI lowering and optimizations

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This results in slightly better code.

  SGPRs: 3552 -> 3608 (1.58 %)
  VGPRs: 1988 -> 2020 (1.61 %)
  Code Size: 178036 -> 177664 (-0.21 %) bytes
  Max Waves: 1136 -> 1136 (0.00 %)

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29313>
This commit is contained in:
Marek Olšák 2024-05-22 12:42:54 -04:00 • committed by Marge Bot
parent 35c5435eae
commit 3ab0e18db4
1 changed files with 11 additions and 5 deletions
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16
src/gallium/drivers/radeonsi/si_shader.c
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@ -2495,6 +2495,17 @@ struct nir_shader *si_get_nir_shader(struct si_shader *shader,
NIR_PASS_V(nir, nir_clear_shared_memory, shared_size, chunk_size);
}
NIR_PASS(progress, nir, ac_nir_lower_intrinsics_to_args, sel->screen->info.gfx_level,
si_select_hw_stage(nir->info.stage, key, sel->screen->info.gfx_level),
&args->ac);
NIR_PASS(progress, nir, si_nir_lower_abi, shader, args);
if (progress) {
si_nir_opts(sel->screen, nir, false);
progress = false;
late_opts = true;
}
NIR_PASS(progress, nir, nir_opt_load_store_vectorize,
&(nir_load_store_vectorize_options){
.modes = nir_var_mem_ssbo | nir_var_mem_ubo | nir_var_mem_shared | nir_var_mem_global |
@ -2509,11 +2520,6 @@ struct nir_shader *si_get_nir_shader(struct si_shader *shader,
NIR_PASS(progress, nir, nir_opt_shrink_stores, false);
NIR_PASS(progress, nir, ac_nir_lower_global_access);
NIR_PASS(progress, nir, ac_nir_lower_intrinsics_to_args, sel->screen->info.gfx_level,
si_select_hw_stage(nir->info.stage, key, sel->screen->info.gfx_level),
&args->ac);
NIR_PASS(progress, nir, si_nir_lower_abi, shader, args);
if (progress) {
si_nir_opts(sel->screen, nir, false);
progress = false;