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radv: move fields to radv_compiler_info::key

Browse source 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41022>
This commit is contained in:
Rhys Perry 2026-04-23 16:13:27 +01:00 • committed by Marge Bot
parent 7c93a6e91c
commit 3aa6903883
12 changed files with 87 additions and 76 deletions
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20
src/amd/vulkan/nir/radv_nir_rt_stage_common.c
View file

@ -268,11 +268,11 @@ radv_build_rt_prolog(const struct radv_compiler_info *compiler_info, struct radv
stage->info.loads_dynamic_offsets = true;
stage->info.force_indirect_descriptors = true;
stage->info.descriptor_heap = uses_descriptor_heap;
stage->info.wave_size = compiler_info->rt_wave_size;
stage->info.wave_size = compiler_info->key.rt_wave_size;
stage->info.workgroup_size = stage->info.wave_size;
stage->info.user_data_0 = R_00B900_COMPUTE_USER_DATA_0;
stage->info.type = RADV_SHADER_TYPE_RT_PROLOG;
stage->info.cs.block_size[0] = compiler_info->rt_wave_size;
stage->info.cs.block_size[0] = compiler_info->key.rt_wave_size;
stage->info.cs.block_size[1] = 1;
stage->info.cs.block_size[2] = 1;
stage->info.cs.uses_thread_id[0] = true;
@ -283,10 +283,10 @@ radv_build_rt_prolog(const struct radv_compiler_info *compiler_info, struct radv
debug);
stage->info.user_sgprs_locs = stage->args.user_sgprs_locs;
b.shader->info.workgroup_size[0] = compiler_info->rt_wave_size;
b.shader->info.api_subgroup_size = compiler_info->rt_wave_size;
b.shader->info.max_subgroup_size = compiler_info->rt_wave_size;
b.shader->info.min_subgroup_size = compiler_info->rt_wave_size;
b.shader->info.workgroup_size[0] = compiler_info->key.rt_wave_size;
b.shader->info.api_subgroup_size = compiler_info->key.rt_wave_size;
b.shader->info.max_subgroup_size = compiler_info->key.rt_wave_size;
b.shader->info.min_subgroup_size = compiler_info->key.rt_wave_size;
nir_function *raygen_function = nir_function_create(b.shader, "raygen_func");
radv_nir_init_rt_function_params(raygen_function, MESA_SHADER_RAYGEN, 0, 0, uses_descriptor_heap);
@ -319,7 +319,7 @@ radv_build_rt_prolog(const struct radv_compiler_info *compiler_info, struct radv
nir_def *local_id = nir_channel(&b, nir_load_local_invocation_id(&b), 0);
nir_def *unswizzled_id_x = nir_iadd(&b, nir_imul_imm(&b, wg_ids[0], compiler_info->rt_wave_size), local_id);
nir_def *unswizzled_id_x = nir_iadd(&b, nir_imul_imm(&b, wg_ids[0], compiler_info->key.rt_wave_size), local_id);
nir_def *unswizzled_id_y = wg_ids[1];
/* Swizzle ray launch IDs. We dispatch a 1D 32x1/64x1 workgroup natively. Many games dispatch
@ -365,7 +365,7 @@ radv_build_rt_prolog(const struct radv_compiler_info *compiler_info, struct radv
swizzled_id_y = nir_bitfield_select(&b, nir_imm_int(&b, 0x3), swizzled_id_y, swizzled_id_shifted_y);
uint32_t workgroup_width = 8;
uint32_t workgroup_height = compiler_info->rt_wave_size == 32 ? 4 : 8;
uint32_t workgroup_height = compiler_info->key.rt_wave_size == 32 ? 4 : 8;
uint32_t workgroup_height_mask = workgroup_height - 1;
/* Fix up the workgroup IDs after converting from 32x1/64x1 to 8x4/8x8. The X dimension of the
@ -375,7 +375,7 @@ radv_build_rt_prolog(const struct radv_compiler_info *compiler_info, struct radv
* the fact we divided the X component of the ID.
*/
nir_def *wg_id_y_rem = nir_iand_imm(&b, wg_ids[1], workgroup_height_mask);
nir_def *new_wg_start_x = nir_imul_imm(&b, wg_ids[0], compiler_info->rt_wave_size);
nir_def *new_wg_start_x = nir_imul_imm(&b, wg_ids[0], compiler_info->key.rt_wave_size);
new_wg_start_x = nir_iadd(&b, new_wg_start_x, nir_imul_imm(&b, wg_id_y_rem, workgroup_width));
nir_def *new_wg_start_y = nir_iand_imm(&b, wg_ids[1], ~workgroup_height_mask);
@ -392,7 +392,7 @@ radv_build_rt_prolog(const struct radv_compiler_info *compiler_info, struct radv
/* If parts of this wave would've exceeded the launch size in the X dimension, their threads will be masked out and
* exec won't equal -1. In that case, using swizzled IDs is invalid.
*/
nir_def *partial_oob_x = nir_ine_imm(&b, nir_ballot(&b, 1, compiler_info->rt_wave_size, nir_imm_true(&b)), -1);
nir_def *partial_oob_x = nir_ine_imm(&b, nir_ballot(&b, 1, compiler_info->key.rt_wave_size, nir_imm_true(&b)), -1);
nir_def *partial_oob_y = nir_uge(&b, wg_ids[1], y_wg_bound);
nir_def *partial_oob = nir_ior(&b, partial_oob_x, partial_oob_y);

2
src/amd/vulkan/nir/radv_nir_rt_stage_monolithic.c
View file

@ -381,7 +381,7 @@ lower_rt_call_monolithic(nir_builder *b, nir_intrinsic_instr *intr, void *data)
nir_pop_if(b, NULL);
b->shader->info.shared_size =
MAX2(b->shader->info.shared_size, compiler_info->rt_wave_size * MAX_STACK_ENTRY_COUNT * sizeof(uint32_t));
MAX2(b->shader->info.shared_size, compiler_info->key.rt_wave_size * MAX_STACK_ENTRY_COUNT * sizeof(uint32_t));
nir_instr_remove(&intr->instr);
return true;

16
src/amd/vulkan/nir/radv_nir_rt_traversal_shader.c
View file

@ -1216,12 +1216,12 @@ radv_build_traversal(const struct radv_compiler_info *compiler_info, struct radv
uint32_t stack_stride;
if (radv_use_bvh_stack_rtn(compiler_info)) {
stack_idx = radv_build_bvh_stack_rtn_addr(b, stack_idx, compiler_info, compiler_info->rt_wave_size, 0,
stack_idx = radv_build_bvh_stack_rtn_addr(b, stack_idx, compiler_info, compiler_info->key.rt_wave_size, 0,
MAX_STACK_ENTRY_COUNT);
stack_stride = 1;
} else {
stack_idx = nir_imul_imm(b, stack_idx, sizeof(uint32_t));
stack_stride = compiler_info->rt_wave_size * sizeof(uint32_t);
stack_stride = compiler_info->key.rt_wave_size * sizeof(uint32_t);
}
nir_store_var(b, data.trav_vars.result.hit, nir_imm_false(b), 1);
@ -1313,11 +1313,11 @@ radv_build_traversal_shader(const struct radv_compiler_info *compiler_info, stru
* invalid variable modes.*/
nir_builder b = radv_meta_nir_init_shader(MESA_SHADER_INTERSECTION, "rt_traversal");
b.shader->options = &compiler_info->nir_options[MESA_SHADER_INTERSECTION];
b.shader->info.workgroup_size[0] = compiler_info->rt_wave_size;
b.shader->info.api_subgroup_size = compiler_info->rt_wave_size;
b.shader->info.max_subgroup_size = compiler_info->rt_wave_size;
b.shader->info.min_subgroup_size = compiler_info->rt_wave_size;
b.shader->info.shared_size = compiler_info->rt_wave_size * MAX_STACK_ENTRY_COUNT * sizeof(uint32_t);
b.shader->info.workgroup_size[0] = compiler_info->key.rt_wave_size;
b.shader->info.api_subgroup_size = compiler_info->key.rt_wave_size;
b.shader->info.max_subgroup_size = compiler_info->key.rt_wave_size;
b.shader->info.min_subgroup_size = compiler_info->key.rt_wave_size;
b.shader->info.shared_size = compiler_info->key.rt_wave_size * MAX_STACK_ENTRY_COUNT * sizeof(uint32_t);
struct radv_nir_rt_traversal_params params = {0};
@ -1365,7 +1365,7 @@ radv_build_traversal_shader(const struct radv_compiler_info *compiler_info, stru
}
b.cursor = nir_after_impl(nir_shader_get_entrypoint(b.shader));
radv_nir_lower_rt_storage(b.shader, hit_attrib_derefs, NULL, NULL, compiler_info->rt_wave_size);
radv_nir_lower_rt_storage(b.shader, hit_attrib_derefs, NULL, NULL, compiler_info->key.rt_wave_size);
nir_push_if(&b, nir_load_var(&b, result.hit));
{

2
src/amd/vulkan/radv_aco_shader_info.h
View file

@ -62,7 +62,7 @@ radv_aco_convert_shader_info(struct aco_shader_info *aco_info, const struct radv
aco_info->ps.spi_ps_input_ena = radv->ps.spi_ps_input_ena;
aco_info->ps.spi_ps_input_addr = radv->ps.spi_ps_input_addr;
aco_info->ps.has_prolog = false;
aco_info->image_2d_view_of_3d = compiler_info->image_2d_view_of_3d;
aco_info->image_2d_view_of_3d = compiler_info->key.image_2d_view_of_3d;
aco_info->epilog_pc = radv_args->epilog_pc;
aco_info->hw_stage = radv_select_hw_stage(radv, compiler_info->ac->gfx_level);
aco_info->next_stage_pc = radv_args->next_stage_pc;

36
src/amd/vulkan/radv_device.c
View file

@ -1149,9 +1149,28 @@ radv_device_init_compiler_info(struct radv_device *device)
.address32_hi = pdev->info.address32_hi,
.rbplus_allowed = pdev->info.rbplus_allowed,
},
/* Misc values included as part of the cache key */
.key =
{
/* Shader features */
.use_llvm = pdev->use_llvm,
.use_ngg = pdev->use_ngg,
.nggc_max_ps_params = nggc_max_ps_params,
.load_grid_size_from_user_sgpr = pdev->load_grid_size_from_user_sgpr,
.emulate_ngg_gs_query_pipeline_stat = pdev->emulate_ngg_gs_query_pipeline_stat,
.primitives_generated_query = device->cache_key.primitives_generated_query,
.mesh_shader_queries = device->cache_key.mesh_shader_queries,
.image_2d_view_of_3d = device->cache_key.image_2d_view_of_3d,
.use_fmask = pdev->use_fmask,
.robust_buffer_access = pdev->use_llvm && (device->vk.enabled_features.robustBufferAccess2 ||
device->vk.enabled_features.robustBufferAccess),
.force_aniso = device->force_aniso,
/* Wave/subgroup sizes */
.ge_wave_size = pdev->ge_wave_size,
.ps_wave_size = pdev->ps_wave_size,
.cs_wave_size = pdev->cs_wave_size,
.rt_wave_size = pdev->rt_wave_size,
},
/* Debug/tracing */
.debug =
@ -1197,29 +1216,14 @@ radv_device_init_compiler_info(struct radv_device *device)
.image_descriptor_alignment = pdev->vk.properties.imageDescriptorAlignment,
.buffer_descriptor_size = pdev->vk.properties.bufferDescriptorSize,
.buffer_descriptor_alignment = pdev->vk.properties.bufferDescriptorAlignment,
/* Shader features */
/* Shader features, included as part of the pipeline key */
.device_robustness_state = &device->vk.robustness_state,
.use_ngg = pdev->use_ngg,
.load_grid_size_from_user_sgpr = pdev->load_grid_size_from_user_sgpr,
.emulate_ngg_gs_query_pipeline_stat = pdev->emulate_ngg_gs_query_pipeline_stat,
.primitives_generated_query = device->cache_key.primitives_generated_query,
.mesh_shader_queries = device->cache_key.mesh_shader_queries,
.image_2d_view_of_3d = device->cache_key.image_2d_view_of_3d,
.use_fmask = pdev->use_fmask,
.smooth_lines = device->vk.enabled_features.smoothLines,
.force_vrs_enabled = device->force_vrs_enabled,
.robust_buffer_access =
(device->vk.enabled_features.robustBufferAccess2 || device->vk.enabled_features.robustBufferAccess),
.force_aniso = device->force_aniso,
.nggc_max_ps_params = nggc_max_ps_params,
/* Wave/subgroup sizes */
.subgroup_size = device->vk.physical->properties.subgroupSize,
.min_subgroup_size = device->vk.physical->properties.minSubgroupSize,
.max_subgroup_size = device->vk.physical->properties.maxSubgroupSize,
.ge_wave_size = pdev->ge_wave_size,
.ps_wave_size = pdev->ps_wave_size,
.cs_wave_size = pdev->cs_wave_size,
.rt_wave_size = pdev->rt_wave_size,
/* NIR/SPIR-V */
.spirv_caps = vk_physical_device_get_spirv_capabilities(device->vk.physical),
};

2
src/amd/vulkan/radv_pipeline.c
View file

@ -494,7 +494,7 @@ radv_postprocess_nir(const struct radv_compiler_info *compiler_info, const struc
.wave_size = stage->info.wave_size,
.workgroup_size = stage->info.workgroup_size,
.use_llvm = use_llvm,
.load_grid_size_from_user_sgpr = compiler_info->load_grid_size_from_user_sgpr,
.load_grid_size_from_user_sgpr = compiler_info->key.load_grid_size_from_user_sgpr,
});
NIR_PASS(_, stage->nir, radv_nir_lower_abi, gfx_level, stage, gfx_state, compiler_info->hw.address32_hi);

2
src/amd/vulkan/radv_pipeline_graphics.c
View file

@ -1735,7 +1735,7 @@ radv_generate_graphics_state_key(const struct radv_compiler_info *compiler_info,
key.dynamic_rasterization_samples = BITSET_TEST(state->dynamic, MESA_VK_DYNAMIC_MS_RASTERIZATION_SAMPLES) ||
(!!(state->shader_stages & VK_SHADER_STAGE_FRAGMENT_BIT) && !state->ms);
if (compiler_info->use_ngg) {
if (compiler_info->key.use_ngg) {
VkShaderStageFlags ngg_stage;
if (state->shader_stages & VK_SHADER_STAGE_GEOMETRY_BIT) {

4
src/amd/vulkan/radv_sampler.c
View file

@ -134,8 +134,8 @@ radv_tex_filter_mode(VkSamplerReductionMode mode)
static uint32_t
radv_get_max_anisotropy(const struct radv_compiler_info *compiler_info, const struct vk_sampler_state *sampler_state)
{
if (compiler_info->force_aniso >= 0)
return compiler_info->force_aniso;
if (compiler_info->key.force_aniso >= 0)
return compiler_info->key.force_aniso;
if (sampler_state->anisotropy_enable && sampler_state->max_anisotropy > 1.0f)
return (uint32_t)sampler_state->max_anisotropy;

26
src/amd/vulkan/radv_shader.c
View file

@ -381,11 +381,11 @@ radv_shader_choose_subgroup_size(const struct radv_compiler_info *compiler_info,
unsigned default_wave_size;
if (nir->info.ray_queries)
default_wave_size = compiler_info->rt_wave_size;
default_wave_size = compiler_info->key.rt_wave_size;
else if (nir->info.stage == MESA_SHADER_MESH)
default_wave_size = compiler_info->ge_wave_size;
default_wave_size = compiler_info->key.ge_wave_size;
else
default_wave_size = compiler_info->cs_wave_size;
default_wave_size = compiler_info->key.cs_wave_size;
/* Games don't always request full subgroups when they should, which can cause bugs if cswave32
* is enabled. Furthermore, if cooperative matrices or subgroup info are used, we can't transparently change
@ -410,13 +410,13 @@ radv_shader_choose_subgroup_size(const struct radv_compiler_info *compiler_info,
wave_size = 64;
} else if (nir->info.stage == MESA_SHADER_FRAGMENT) {
if (nir->info.ray_queries)
wave_size = compiler_info->rt_wave_size;
wave_size = compiler_info->key.rt_wave_size;
else
wave_size = compiler_info->ps_wave_size;
wave_size = compiler_info->key.ps_wave_size;
} else if (mesa_shader_stage_is_rt(nir->info.stage)) {
wave_size = compiler_info->rt_wave_size;
wave_size = compiler_info->key.rt_wave_size;
} else {
wave_size = compiler_info->ge_wave_size;
wave_size = compiler_info->key.ge_wave_size;
}
if (nir->info.api_subgroup_size == 0) {
@ -428,7 +428,7 @@ radv_shader_choose_subgroup_size(const struct radv_compiler_info *compiler_info,
/* We might still decide to use ngg later. */
if (nir->info.stage == MESA_SHADER_GEOMETRY)
nir->info.min_subgroup_size = compiler_info->ge_wave_size;
nir->info.min_subgroup_size = compiler_info->key.ge_wave_size;
else
nir->info.min_subgroup_size = wave_size;
}
@ -696,7 +696,7 @@ radv_shader_spirv_to_nir(const struct radv_compiler_info *compiler_info, struct
.lower_txf_offset = true,
.lower_tg4_offsets = true,
.lower_txs_cube_array = true,
.lower_to_fragment_fetch_amd = compiler_info->use_fmask,
.lower_to_fragment_fetch_amd = compiler_info->key.use_fmask,
.lower_lod_zero_width = true,
.lower_invalid_implicit_lod = true,
.lower_1d = compiler_info->ac->gfx_level == GFX9,
@ -895,8 +895,8 @@ radv_consider_culling(const struct radv_compiler_info *compiler_info, struct nir
return false;
/* TODO: consider other heuristics here, such as PS execution time */
assert(compiler_info->nggc_max_ps_params);
if (util_bitcount64(ps_inputs_read) > compiler_info->nggc_max_ps_params)
assert(compiler_info->key.nggc_max_ps_params);
if (util_bitcount64(ps_inputs_read) > compiler_info->key.nggc_max_ps_params)
return false;
/* Only triangle culling is supported. */
@ -3284,7 +3284,7 @@ radv_fill_nir_compiler_options(const struct radv_compiler_info *compiler_info,
options->family = compiler_info->hw.family;
options->address32_hi = compiler_info->hw.address32_hi;
/* robust_buffer_access_llvm here used by LLVM only, pipeline robustness is not exposed there. */
options->robust_buffer_access_llvm = compiler_info->robust_buffer_access;
options->robust_buffer_access_llvm = compiler_info->key.robust_buffer_access;
options->wgp_mode = should_use_wgp;
options->dump_shader = can_dump_shader;
options->dump_ir = options->dump_shader && compiler_info->debug.dump_backend_ir;
@ -3840,7 +3840,7 @@ radv_get_tess_wg_info(const struct radv_compiler_info *compiler_info, const ac_n
{
const uint32_t lds_input_vertex_size = get_tcs_input_vertex_stride(tcs_num_lds_inputs);
ac_nir_compute_tess_wg_info(compiler_info->ac, io_info, tcs_vertices_out, compiler_info->ge_wave_size, false,
ac_nir_compute_tess_wg_info(compiler_info->ac, io_info, tcs_vertices_out, compiler_info->key.ge_wave_size, false,
tcs_num_input_vertices, lds_input_vertex_size, 0, num_patches_per_wg, lds_size);
}

43
src/amd/vulkan/radv_shader.h
View file

@ -520,8 +520,28 @@ struct radv_compiler_info {
bool rbplus_allowed;
} hw;
/* Misc values included as part of the cache key */
struct {
bool use_llvm;
/* Shader features */
uint32_t use_llvm : 1;
uint32_t use_ngg : 1;
uint32_t nggc_max_ps_params : 4;
uint32_t load_grid_size_from_user_sgpr : 1;
uint32_t emulate_ngg_gs_query_pipeline_stat : 1;
uint32_t primitives_generated_query : 1;
uint32_t mesh_shader_queries : 1;
uint32_t image_2d_view_of_3d : 1;
uint32_t use_fmask : 1;
uint32_t robust_buffer_access : 1; /* Only used by LLVM. */
uint32_t padding : 19;
int32_t force_aniso;
/* Wave/subgroup sizes */
uint8_t ge_wave_size;
uint8_t ps_wave_size;
uint8_t cs_wave_size;
uint8_t rt_wave_size;
} key;
/* Debug/tracing */
@ -558,8 +578,7 @@ struct radv_compiler_info {
uint8_t override_graphics_shader_version;
uint8_t override_ray_tracing_shader_version;
/* Shader features */
const struct vk_pipeline_robustness_state *device_robustness_state;
/* Descriptors */
uint8_t sampled_image_desc_size;
uint8_t combined_image_sampler_desc_size;
uint8_t combined_image_sampler_offset;
@ -569,33 +588,21 @@ struct radv_compiler_info {
uint32_t image_descriptor_alignment;
uint32_t buffer_descriptor_size;
uint32_t buffer_descriptor_alignment;
bool use_ngg;
bool load_grid_size_from_user_sgpr;
bool emulate_ngg_gs_query_pipeline_stat;
bool primitives_generated_query;
bool mesh_shader_queries;
bool image_2d_view_of_3d;
bool use_fmask;
/* Shader features, included as part of the pipeline key */
const struct vk_pipeline_robustness_state *device_robustness_state;
bool smooth_lines;
bool force_vrs_enabled;
bool robust_buffer_access; /* Only used by LLVM. */
int force_aniso;
uint8_t nggc_max_ps_params;
/* Wave/subgroup sizes */
uint32_t subgroup_size;
uint32_t min_subgroup_size;
uint32_t max_subgroup_size;
uint8_t ge_wave_size;
uint8_t ps_wave_size;
uint8_t cs_wave_size;
uint8_t rt_wave_size;
/* NIR/SPIR-V */
struct spirv_capabilities spirv_caps;
nir_shader_compiler_options nir_options[MESA_VULKAN_SHADER_STAGES];
};
struct radv_shader_stage;
void radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively);

2
src/amd/vulkan/radv_shader_args.c
View file

@ -612,7 +612,7 @@ declare_shader_args(const struct radv_compiler_info *compiler_info, struct radv_
declare_global_input_sgprs(state, gfx_level, info, user_sgpr_info);
if (info->cs.uses_grid_size) {
if (compiler_info->load_grid_size_from_user_sgpr)
if (compiler_info->key.load_grid_size_from_user_sgpr)
RADV_ADD_UD_ARG(state, 3, AC_ARG_VALUE, ac.num_work_groups, AC_UD_CS_GRID_SIZE);
else
RADV_ADD_UD_ARG(state, 2, AC_ARG_CONST_ADDR, ac.num_work_groups, AC_UD_CS_GRID_SIZE);

8
src/amd/vulkan/radv_shader_info.c
View file

@ -484,9 +484,9 @@ static void
gather_shader_info_ngg_query(const struct radv_compiler_info *compiler_info, struct radv_shader_info *info)
{
info->gs.has_pipeline_stat_query =
compiler_info->emulate_ngg_gs_query_pipeline_stat && info->stage == MESA_SHADER_GEOMETRY;
compiler_info->key.emulate_ngg_gs_query_pipeline_stat && info->stage == MESA_SHADER_GEOMETRY;
info->has_xfb_query = !!info->so.enabled_stream_buffers_mask;
info->has_prim_query = compiler_info->primitives_generated_query || info->has_xfb_query;
info->has_prim_query = compiler_info->key.primitives_generated_query || info->has_xfb_query;
}
uint64_t
@ -754,7 +754,7 @@ gather_shader_info_mesh(const struct radv_compiler_info *compiler_info, const ni
ngg_info->prim_amp_factor = nir->info.mesh.max_primitives_out;
ngg_info->vgt_esgs_ring_itemsize = 1;
info->ms.has_query = compiler_info->mesh_shader_queries;
info->ms.has_query = compiler_info->key.mesh_shader_queries;
info->ms.has_task = stage_key->has_task_shader;
}
@ -900,7 +900,7 @@ gather_shader_info_task(const struct radv_compiler_info *compiler_info, const ni
info->cs.linear_taskmesh_dispatch =
nir->info.mesh.ts_mesh_dispatch_dimensions[1] == 1 && nir->info.mesh.ts_mesh_dispatch_dimensions[2] == 1;
info->cs.has_query = compiler_info->mesh_shader_queries;
info->cs.has_query = compiler_info->key.mesh_shader_queries;
}
static uint32_t