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First step of Radeon DRI unification:

Browse source 
- Makes all three drivers use the same screen structure and setup code, with a
  few ifdefs for the separate compilation to deal with symbols not being
  available to all drivers and the fact that we have no mechanism for dealing
  with different config options for different chip families in the same driver.
  These issues should be dealt with later.
- Introduces IS_R[123]00_CLASS(radeonScreenPtr) macro for code for taking
  different paths depending on the general class of chipset.
- Adds many new R300-class PCI IDs, though not all those listed in
  radeon_driver.c.
This commit is contained in:
Eric Anholt 2005-11-02 01:15:07 +00:00
parent a9b927cb6e
commit 3a5626cb84
30 changed files with 611 additions and 1993 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

15
src/mesa/drivers/dri/r200/Makefile
View file

@ -14,7 +14,6 @@ endif
DRIVER_SOURCES = r200_context.c \
r200_ioctl.c \
r200_lock.c \
r200_screen.c \
r200_state.c \
r200_state_init.c \
r200_cmdbuf.c \
@ -32,12 +31,15 @@ DRIVER_SOURCES = r200_context.c \
r200_vtxfmt_sse.c \
r200_vtxfmt_x86.c \
r200_fragshader.c \
radeon_screen.c \
$(EGL_SOURCES)
C_SOURCES = $(COMMON_SOURCES) $(DRIVER_SOURCES)
X86_SOURCES = r200_vtxtmp_x86.S
DEFINES += -DRADEON_COMMON=1 -DRADEON_COMMON_FOR_R200
SYMLINKS = \
server/radeon_egl.c \
server/radeon_dri.c \
@ -46,6 +48,11 @@ SYMLINKS = \
server/radeon_macros.h \
server/radeon_reg.h
COMMON_SYMLINKS = \
radeon_chipset.h \
radeon_screen.c \
radeon_screen.h
##### TARGETS #####
@ -59,5 +66,9 @@ server:
$(SYMLINKS): server
@[ -e $@ ] || ln -sf ../../radeon/$@ server/
symlinks: $(SYMLINKS)
$(COMMON_SYMLINKS):
@[ -e $@ ] || ln -sf ../radeon/$@ ./
symlinks: $(SYMLINKS) $(COMMON_SYMLINKS)

14
src/mesa/drivers/dri/r200/r200_context.c
View file

@ -263,7 +263,7 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual,
void *sharedContextPrivate)
{
__DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
r200ScreenPtr screen = (r200ScreenPtr)(sPriv->private);
radeonScreenPtr screen = (radeonScreenPtr)(sPriv->private);
struct dd_function_table functions;
r200ContextPtr rmesa;
GLcontext *ctx, *shareCtx;
@ -344,7 +344,7 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual,
make_empty_list( & rmesa->swapped );
rmesa->nr_heaps = 1 /* screen->numTexHeaps */ ;
assert(rmesa->nr_heaps < R200_NR_TEX_HEAPS);
assert(rmesa->nr_heaps < RADEON_NR_TEX_HEAPS);
for ( i = 0 ; i < rmesa->nr_heaps ; i++ ) {
rmesa->texture_heaps[i] = driCreateTextureHeap( i, rmesa,
screen->texSize[i],
@ -455,7 +455,7 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual,
_math_matrix_set_identity( &rmesa->tmpmat );
driInitExtensions( ctx, card_extensions, GL_TRUE );
if (!(rmesa->r200Screen->chipset & R200_CHIPSET_YCBCR_BROKEN)) {
if (!(rmesa->r200Screen->chip_flags & R200_CHIPSET_YCBCR_BROKEN)) {
/* yuv textures don't work with some chips - R200 / rv280 okay so far
others get the bit ordering right but don't actually do YUV-RGB conversion */
_mesa_enable_extension( ctx, "GL_MESA_ycbcr_texture" );
@ -533,15 +533,15 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual,
FALLBACK(rmesa, R200_FALLBACK_DISABLE, 1);
}
else if (tcl_mode == DRI_CONF_TCL_SW || getenv("R200_NO_TCL") ||
!(rmesa->r200Screen->chipset & R200_CHIPSET_TCL)) {
if (rmesa->r200Screen->chipset & R200_CHIPSET_TCL) {
rmesa->r200Screen->chipset &= ~R200_CHIPSET_TCL;
!(rmesa->r200Screen->chip_flags & RADEON_CHIPSET_TCL)) {
if (rmesa->r200Screen->chip_flags & RADEON_CHIPSET_TCL) {
rmesa->r200Screen->chip_flags &= ~RADEON_CHIPSET_TCL;
fprintf(stderr, "Disabling HW TCL support\n");
}
TCL_FALLBACK(rmesa->glCtx, R200_TCL_FALLBACK_TCL_DISABLE, 1);
}
if (rmesa->r200Screen->chipset & R200_CHIPSET_TCL) {
if (rmesa->r200Screen->chip_flags & RADEON_CHIPSET_TCL) {
if (tcl_mode >= DRI_CONF_TCL_VTXFMT)
r200VtxfmtInit( ctx, tcl_mode >= DRI_CONF_TCL_CODEGEN );

6
src/mesa/drivers/dri/r200/r200_context.h
View file

@ -54,7 +54,7 @@ typedef struct r200_context r200ContextRec;
typedef struct r200_context *r200ContextPtr;
#include "r200_lock.h"
#include "r200_screen.h"
#include "radeon_screen.h"
#include "mm.h"
/* Flags for software fallback cases */
@ -883,7 +883,7 @@ struct r200_context {
/* Texture object bookkeeping
*/
unsigned nr_heaps;
driTexHeap * texture_heaps[ R200_NR_TEX_HEAPS ];
driTexHeap * texture_heaps[ RADEON_NR_TEX_HEAPS ];
driTextureObject swapped;
int texture_depth;
float initialMaxAnisotropy;
@ -927,7 +927,7 @@ struct r200_context {
unsigned int lastStamp;
GLboolean lost_context;
GLboolean save_on_next_emit;
r200ScreenPtr r200Screen; /* Screen private DRI data */
radeonScreenPtr r200Screen; /* Screen private DRI data */
drm_radeon_sarea_t *sarea; /* Private SAREA data */
/* TCL stuff

2
src/mesa/drivers/dri/r200/r200_ioctl.c
View file

@ -635,7 +635,7 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask, GLboolean all,
if (rmesa->using_hyperz) {
flags |= RADEON_USE_COMP_ZBUF;
/* if (rmesa->r200Screen->chipset & R200_CHIPSET_REAL_R200)
/* if (rmesa->r200Screen->chip_family == CHIP_FAMILY_R200)
flags |= RADEON_USE_HIERZ; */
if (!(rmesa->state.stencil.hwBuffer) ||
((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) &&

755
src/mesa/drivers/dri/r200/r200_screen.c
View file

@ -1,755 +0,0 @@
/* $XFree86: xc/lib/GL/mesa/src/drv/r200/r200_screen.c,v 1.4 2003/05/08 09:25:35 herrb Exp $ */
/*
Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
The Weather Channel (TM) funded Tungsten Graphics to develop the
initial release of the Radeon 8500 driver under the XFree86 license.
This notice must be preserved.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************/
/**
* \file r200_screen.c
* Screen initialization functions for the R200 driver.
*
* \author Keith Whitwell <keith@tungstengraphics.com>
*/
#include <dlfcn.h>
#include "glheader.h"
#include "imports.h"
#include "context.h"
#include "framebuffer.h"
#include "renderbuffer.h"
#define STANDALONE_MMIO
#include "r200_screen.h"
#include "r200_context.h"
#include "r200_ioctl.h"
#include "r200_span.h"
#include "radeon_macros.h"
#include "radeon_reg.h"
#include "drirenderbuffer.h"
#include "utils.h"
#include "vblank.h"
#include "GL/internal/dri_interface.h"
/* R200 configuration
*/
#include "xmlpool.h"
PUBLIC const char __driConfigOptions[] =
DRI_CONF_BEGIN
DRI_CONF_SECTION_PERFORMANCE
DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
DRI_CONF_MAX_TEXTURE_UNITS(4,2,6)
DRI_CONF_HYPERZ(false)
DRI_CONF_SECTION_END
DRI_CONF_SECTION_QUALITY
DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
DRI_CONF_NO_NEG_LOD_BIAS(false)
DRI_CONF_FORCE_S3TC_ENABLE(false)
DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
DRI_CONF_TEXTURE_LEVEL_HACK(false)
DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
DRI_CONF_SECTION_END
DRI_CONF_SECTION_DEBUG
DRI_CONF_NO_RAST(false)
DRI_CONF_SECTION_END
DRI_CONF_SECTION_SOFTWARE
DRI_CONF_ARB_VERTEX_PROGRAM(false)
DRI_CONF_NV_VERTEX_PROGRAM(false)
DRI_CONF_SECTION_END
DRI_CONF_END;
static const GLuint __driNConfigOptions = 17;
extern const struct dri_extension card_extensions[];
extern const struct dri_extension blend_extensions[];
extern const struct dri_extension ARB_vp_extension[];
extern const struct dri_extension NV_vp_extension[];
extern const struct dri_extension ATI_fs_extension[];
#if 1
/* Including xf86PciInfo.h introduces a bunch of errors...
*/
#define PCI_CHIP_RS300_5834 0x5834 /* All RS300's are R200 */
#define PCI_CHIP_RS300_5835 0x5835
#define PCI_CHIP_RS300_5836 0x5836
#define PCI_CHIP_RS300_5837 0x5837
#define PCI_CHIP_R200_BB 0x4242 /* r200 (non-derived) start */
#define PCI_CHIP_R200_BC 0x4243
#define PCI_CHIP_R200_QH 0x5148
#define PCI_CHIP_R200_QI 0x5149
#define PCI_CHIP_R200_QJ 0x514A
#define PCI_CHIP_R200_QK 0x514B
#define PCI_CHIP_R200_QL 0x514C
#define PCI_CHIP_R200_QM 0x514D
#define PCI_CHIP_R200_QN 0x514E
#define PCI_CHIP_R200_QO 0x514F /* r200 (non-derived) end */
/* are the R200 Qh (0x5168) and following needed too? They are not in
xf86PciInfo.h but in the pci database. Maybe just secondary ports or
something ? Ah well, better be safe than sorry */
#define PCI_CHIP_R200_Qh 0x5168
#define PCI_CHIP_R200_Qi 0x5169
#define PCI_CHIP_R200_Qj 0x516A
#define PCI_CHIP_R200_Qk 0x516B
#define PCI_CHIP_R200_Ql 0x516C
#define PCI_CHIP_RV250_Id 0x4964
#define PCI_CHIP_RV250_Ie 0x4965
#define PCI_CHIP_RV250_If 0x4966
#define PCI_CHIP_RV250_Ig 0x4967
#define PCI_CHIP_RV250_Ld 0x4C64
#define PCI_CHIP_RV250_Le 0x4C65
#define PCI_CHIP_RV250_Lf 0x4C66
#define PCI_CHIP_RV250_Lg 0x4C67
#define PCI_CHIP_RV280_5960 0x5960
#define PCI_CHIP_RV280_5961 0x5961
#define PCI_CHIP_RV280_5962 0x5962
#define PCI_CHIP_RV280_5963 0x5963
#define PCI_CHIP_RV280_5964 0x5964
#define PCI_CHIP_RV280_5968 0x5968
#define PCI_CHIP_RV280_596A 0x596A
#define PCI_CHIP_RV280_596B 0x596B
#define PCI_CHIP_RV280_5C61 0x5C61
#define PCI_CHIP_RV280_5C62 0x5C62
#define PCI_CHIP_RV280_5C63 0x5C63
#define PCI_CHIP_RV280_5C64 0x5C64
#endif
static r200ScreenPtr __r200Screen;
static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo );
static __GLcontextModes *
r200FillInModes( unsigned pixel_bits, unsigned depth_bits,
unsigned stencil_bits, GLboolean have_back_buffer )
{
__GLcontextModes * modes;
__GLcontextModes * m;
unsigned num_modes;
unsigned depth_buffer_factor;
unsigned back_buffer_factor;
GLenum fb_format;
GLenum fb_type;
/* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
* enough to add support. Basically, if a context is created with an
* fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
* will never be used.
*/
static const GLenum back_buffer_modes[] = {
GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
};
u_int8_t depth_bits_array[2];
u_int8_t stencil_bits_array[2];
depth_bits_array[0] = depth_bits;
depth_bits_array[1] = depth_bits;
/* Just like with the accumulation buffer, always provide some modes
* with a stencil buffer. It will be a sw fallback, but some apps won't
* care about that.
*/
stencil_bits_array[0] = 0;
stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits;
depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1;
back_buffer_factor = (have_back_buffer) ? 2 : 1;
num_modes = depth_buffer_factor * back_buffer_factor * 4;
if ( pixel_bits == 16 ) {
fb_format = GL_RGB;
fb_type = GL_UNSIGNED_SHORT_5_6_5;
}
else {
fb_format = GL_BGRA;
fb_type = GL_UNSIGNED_INT_8_8_8_8_REV;
}
modes = (*dri_interface->createContextModes)( num_modes, sizeof( __GLcontextModes ) );
m = modes;
if ( ! driFillInModes( & m, fb_format, fb_type,
depth_bits_array, stencil_bits_array, depth_buffer_factor,
back_buffer_modes, back_buffer_factor,
GLX_TRUE_COLOR ) ) {
fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
__func__, __LINE__ );
return NULL;
}
if ( ! driFillInModes( & m, fb_format, fb_type,
depth_bits_array, stencil_bits_array, depth_buffer_factor,
back_buffer_modes, back_buffer_factor,
GLX_DIRECT_COLOR ) ) {
fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
__func__, __LINE__ );
return NULL;
}
/* Mark the visual as slow if there are "fake" stencil bits.
*/
for ( m = modes ; m != NULL ; m = m->next ) {
if ( (m->stencilBits != 0) && (m->stencilBits != stencil_bits) ) {
m->visualRating = GLX_SLOW_CONFIG;
}
}
return modes;
}
/* Create the device specific screen private data struct.
*/
static r200ScreenPtr
r200CreateScreen( __DRIscreenPrivate *sPriv )
{
r200ScreenPtr screen;
RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv;
unsigned char *RADEONMMIO;
PFNGLXSCRENABLEEXTENSIONPROC glx_enable_extension =
(PFNGLXSCRENABLEEXTENSIONPROC) (*dri_interface->getProcAddress("glxEnableExtension"));
void * const psc = sPriv->psc->screenConfigs;
if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) {
fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n");
return GL_FALSE;
}
/* Allocate the private area */
screen = (r200ScreenPtr) CALLOC( sizeof(*screen) );
if ( !screen ) {
__driUtilMessage("%s: Could not allocate memory for screen structure",
__FUNCTION__);
return NULL;
}
screen->chipset = 0;
switch ( dri_priv->deviceID ) {
case PCI_CHIP_R200_BB:
case PCI_CHIP_R200_BC:
case PCI_CHIP_R200_QH:
case PCI_CHIP_R200_QI:
case PCI_CHIP_R200_QJ:
case PCI_CHIP_R200_QK:
case PCI_CHIP_R200_QL:
case PCI_CHIP_R200_QM:
case PCI_CHIP_R200_QN:
case PCI_CHIP_R200_QO:
case PCI_CHIP_R200_Qh:
case PCI_CHIP_R200_Qi:
case PCI_CHIP_R200_Qj:
case PCI_CHIP_R200_Qk:
case PCI_CHIP_R200_Ql:
screen->chipset |= R200_CHIPSET_REAL_R200;
screen->chipset |= R200_CHIPSET_TCL;
break;
case PCI_CHIP_RV250_Id:
case PCI_CHIP_RV250_Ie:
case PCI_CHIP_RV250_If:
case PCI_CHIP_RV250_Ig:
case PCI_CHIP_RV250_Ld:
case PCI_CHIP_RV250_Le:
case PCI_CHIP_RV250_Lf:
case PCI_CHIP_RV250_Lg:
screen->chipset |= R200_CHIPSET_YCBCR_BROKEN;
screen->chipset |= R200_CHIPSET_TCL;
break;
case PCI_CHIP_RV280_5960:
case PCI_CHIP_RV280_5961:
case PCI_CHIP_RV280_5962:
case PCI_CHIP_RV280_5963:
case PCI_CHIP_RV280_5964:
case PCI_CHIP_RV280_5968:
case PCI_CHIP_RV280_596A:
case PCI_CHIP_RV280_596B:
case PCI_CHIP_RV280_5C61:
case PCI_CHIP_RV280_5C62:
case PCI_CHIP_RV280_5C63:
case PCI_CHIP_RV280_5C64:
screen->chipset |= R200_CHIPSET_TCL;
break;
case PCI_CHIP_RS300_5834:
case PCI_CHIP_RS300_5835:
case PCI_CHIP_RS300_5836:
case PCI_CHIP_RS300_5837:
break;
default:
__driUtilMessage("r200CreateScreen(): Device isn't an r200!\n");
FREE( screen );
return NULL;
break;
}
/* parse information in __driConfigOptions */
driParseOptionInfo (&screen->optionCache,
__driConfigOptions, __driNConfigOptions);
/* This is first since which regions we map depends on whether or
* not we are using a PCI card.
*/
screen->IsPCI = dri_priv->IsPCI;
{
int ret;
drm_radeon_getparam_t gp;
gp.param = RADEON_PARAM_GART_BUFFER_OFFSET;
gp.value = &screen->gart_buffer_offset;
ret = drmCommandWriteRead( sPriv->fd, DRM_RADEON_GETPARAM,
&gp, sizeof(gp));
if (ret) {
FREE( screen );
fprintf(stderr, "drmRadeonGetParam (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
return NULL;
}
if (sPriv->drmMinor >= 6) {
gp.param = RADEON_PARAM_GART_BASE;
gp.value = &screen->gart_base;
ret = drmCommandWriteRead( sPriv->fd, DRM_RADEON_GETPARAM,
&gp, sizeof(gp));
if (ret) {
FREE( screen );
fprintf(stderr, "drmR200GetParam (RADEON_PARAM_GART_BASE): %d\n", ret);
return NULL;
}
gp.param = RADEON_PARAM_IRQ_NR;
gp.value = &screen->irq;
ret = drmCommandWriteRead( sPriv->fd, DRM_RADEON_GETPARAM,
&gp, sizeof(gp));
if (ret) {
FREE( screen );
fprintf(stderr, "drmRadeonGetParam (RADEON_PARAM_IRQ_NR): %d\n", ret);
return NULL;
}
/* Check if kernel module is new enough to support cube maps */
screen->drmSupportsCubeMaps = (sPriv->drmMinor >= 7);
/* Check if kernel module is new enough to support blend color and
separate blend functions/equations */
screen->drmSupportsBlendColor = (sPriv->drmMinor >= 11);
screen->drmSupportsTriPerf = (sPriv->drmMinor >= 16);
screen->drmSupportsFragShader = (sPriv->drmMinor >= 18);
screen->drmSupportsPointSprites = (sPriv->drmMinor >= 13);
}
/* Check if ddx has set up a surface reg to cover depth buffer */
screen->depthHasSurface = (sPriv->ddxMajor > 4);
}
screen->mmio.handle = dri_priv->registerHandle;
screen->mmio.size = dri_priv->registerSize;
if ( drmMap( sPriv->fd,
screen->mmio.handle,
screen->mmio.size,
&screen->mmio.map ) ) {
FREE( screen );
__driUtilMessage("%s: drmMap failed\n", __FUNCTION__ );
return NULL;
}
RADEONMMIO = screen->mmio.map;
screen->status.handle = dri_priv->statusHandle;
screen->status.size = dri_priv->statusSize;
if ( drmMap( sPriv->fd,
screen->status.handle,
screen->status.size,
&screen->status.map ) ) {
drmUnmap( screen->mmio.map, screen->mmio.size );
FREE( screen );
__driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ );
return NULL;
}
screen->scratch = (__volatile__ u_int32_t *)
((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
screen->buffers = drmMapBufs( sPriv->fd );
if ( !screen->buffers ) {
drmUnmap( screen->status.map, screen->status.size );
drmUnmap( screen->mmio.map, screen->mmio.size );
FREE( screen );
__driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ );
return NULL;
}
RADEONMMIO = screen->mmio.map;
if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) {
screen->gartTextures.handle = dri_priv->gartTexHandle;
screen->gartTextures.size = dri_priv->gartTexMapSize;
if ( drmMap( sPriv->fd,
screen->gartTextures.handle,
screen->gartTextures.size,
(drmAddressPtr)&screen->gartTextures.map ) ) {
drmUnmapBufs( screen->buffers );
drmUnmap( screen->status.map, screen->status.size );
drmUnmap( screen->mmio.map, screen->mmio.size );
FREE( screen );
__driUtilMessage("%s: drmMAP failed for GART texture area\n", __FUNCTION__);
return NULL;
}
screen->gart_texture_offset = dri_priv->gartTexOffset + ( screen->IsPCI
? INREG( RADEON_AIC_LO_ADDR )
: ( ( INREG( RADEON_MC_AGP_LOCATION ) & 0x0ffffU ) << 16 ) );
}
screen->cpp = dri_priv->bpp / 8;
screen->AGPMode = dri_priv->AGPMode;
screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff ) << 16;
if ( sPriv->drmMinor >= 10 ) {
drm_radeon_setparam_t sp;
sp.param = RADEON_SETPARAM_FB_LOCATION;
sp.value = screen->fbLocation;
drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM,
&sp, sizeof( sp ) );
}
screen->frontOffset = dri_priv->frontOffset;
screen->frontPitch = dri_priv->frontPitch;
screen->backOffset = dri_priv->backOffset;
screen->backPitch = dri_priv->backPitch;
screen->depthOffset = dri_priv->depthOffset;
screen->depthPitch = dri_priv->depthPitch;
screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
+ screen->fbLocation;
screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
dri_priv->log2TexGran;
if ( !screen->gartTextures.map ) {
screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1;
screen->texOffset[RADEON_GART_TEX_HEAP] = 0;
screen->texSize[RADEON_GART_TEX_HEAP] = 0;
screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0;
} else {
screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset;
screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize;
screen->logTexGranularity[RADEON_GART_TEX_HEAP] =
dri_priv->log2GARTTexGran;
}
screen->driScreen = sPriv;
screen->sarea_priv_offset = dri_priv->sarea_priv_offset;
if ( glx_enable_extension != NULL ) {
if ( screen->irq != 0 ) {
(*glx_enable_extension)( psc, "GLX_SGI_swap_control" );
(*glx_enable_extension)( psc, "GLX_SGI_video_sync" );
(*glx_enable_extension)( psc, "GLX_MESA_swap_control" );
}
(*glx_enable_extension)( psc, "GLX_MESA_swap_frame_usage" );
(*glx_enable_extension)( psc, "GLX_MESA_allocate_memory" );
}
sPriv->psc->allocateMemory = (void *) r200AllocateMemoryMESA;
sPriv->psc->freeMemory = (void *) r200FreeMemoryMESA;
sPriv->psc->memoryOffset = (void *) r200GetMemoryOffsetMESA;
return screen;
}
/* Destroy the device specific screen private data struct.
*/
static void
r200DestroyScreen( __DRIscreenPrivate *sPriv )
{
r200ScreenPtr screen = (r200ScreenPtr)sPriv->private;
if (!screen)
return;
if ( screen->gartTextures.map ) {
drmUnmap( screen->gartTextures.map, screen->gartTextures.size );
}
drmUnmapBufs( screen->buffers );
drmUnmap( screen->status.map, screen->status.size );
drmUnmap( screen->mmio.map, screen->mmio.size );
/* free all option information */
driDestroyOptionInfo (&screen->optionCache);
FREE( screen );
sPriv->private = NULL;
}
/* Initialize the driver specific screen private data.
*/
static GLboolean
r200InitDriver( __DRIscreenPrivate *sPriv )
{
__r200Screen = r200CreateScreen( sPriv );
sPriv->private = (void *) __r200Screen;
return sPriv->private ? GL_TRUE : GL_FALSE;
}
/**
* Create and initialize the Mesa and driver specific pixmap buffer
* data. This is called to setup rendering to a particular window.
*
* \todo This function (and its interface) will need to be updated to support
* pbuffers.
*/
static GLboolean
r200CreateBuffer( __DRIscreenPrivate *driScrnPriv,
__DRIdrawablePrivate *driDrawPriv,
const __GLcontextModes *mesaVis,
GLboolean isPixmap )
{
r200ScreenPtr screen = (r200ScreenPtr) driScrnPriv->private;
if (isPixmap) {
return GL_FALSE; /* not implemented */
}
else {
const GLboolean swDepth = GL_FALSE;
const GLboolean swAlpha = GL_FALSE;
const GLboolean swAccum = mesaVis->accumRedBits > 0;
const GLboolean swStencil = mesaVis->stencilBits > 0 &&
mesaVis->depthBits != 24;
struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis);
/* front color renderbuffer */
{
driRenderbuffer *frontRb
= driNewRenderbuffer(GL_RGBA,
driScrnPriv->pFB + screen->frontOffset,
screen->cpp,
screen->frontOffset, screen->frontPitch,
driDrawPriv);
r200SetSpanFunctions(frontRb, mesaVis);
_mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &frontRb->Base);
}
/* back color renderbuffer */
if (mesaVis->doubleBufferMode) {
driRenderbuffer *backRb
= driNewRenderbuffer(GL_RGBA,
driScrnPriv->pFB + screen->backOffset,
screen->cpp,
screen->backOffset, screen->backPitch,
driDrawPriv);
r200SetSpanFunctions(backRb, mesaVis);
_mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &backRb->Base);
}
/* depth renderbuffer */
if (mesaVis->depthBits == 16) {
driRenderbuffer *depthRb
= driNewRenderbuffer(GL_DEPTH_COMPONENT16,
driScrnPriv->pFB + screen->depthOffset,
screen->cpp,
screen->depthOffset, screen->depthPitch,
driDrawPriv);
r200SetSpanFunctions(depthRb, mesaVis);
_mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
depthRb->depthHasSurface = screen->depthHasSurface;
}
else if (mesaVis->depthBits == 24) {
driRenderbuffer *depthRb
= driNewRenderbuffer(GL_DEPTH_COMPONENT24,
driScrnPriv->pFB + screen->depthOffset,
screen->cpp,
screen->depthOffset, screen->depthPitch,
driDrawPriv);
r200SetSpanFunctions(depthRb, mesaVis);
_mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
depthRb->depthHasSurface = screen->depthHasSurface;
}
/* stencil renderbuffer */
if (mesaVis->stencilBits > 0 && !swStencil) {
driRenderbuffer *stencilRb
= driNewRenderbuffer(GL_STENCIL_INDEX8_EXT,
driScrnPriv->pFB + screen->depthOffset,
screen->cpp,
screen->depthOffset, screen->depthPitch,
driDrawPriv);
r200SetSpanFunctions(stencilRb, mesaVis);
_mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencilRb->Base);
stencilRb->depthHasSurface = screen->depthHasSurface;
}
_mesa_add_soft_renderbuffers(fb,
GL_FALSE, /* color */
swDepth,
swStencil,
swAccum,
swAlpha,
GL_FALSE /* aux */);
driDrawPriv->driverPrivate = (void *) fb;
return (driDrawPriv->driverPrivate != NULL);
}
}
static void
r200DestroyBuffer(__DRIdrawablePrivate *driDrawPriv)
{
_mesa_destroy_framebuffer((GLframebuffer *) (driDrawPriv->driverPrivate));
}
static const struct __DriverAPIRec r200API = {
.InitDriver = r200InitDriver,
.DestroyScreen = r200DestroyScreen,
.CreateContext = r200CreateContext,
.DestroyContext = r200DestroyContext,
.CreateBuffer = r200CreateBuffer,
.DestroyBuffer = r200DestroyBuffer,
.SwapBuffers = r200SwapBuffers,
.MakeCurrent = r200MakeCurrent,
.UnbindContext = r200UnbindContext,
.GetSwapInfo = getSwapInfo,
.GetMSC = driGetMSC32,
.WaitForMSC = driWaitForMSC32,
.WaitForSBC = NULL,
.SwapBuffersMSC = NULL
};
/**
* This is the bootstrap function for the driver. libGL supplies all of the
* requisite information about the system, and the driver initializes itself.
* This routine also fills in the linked list pointed to by \c driver_modes
* with the \c __GLcontextModes that the driver can support for windows or
* pbuffers.
*
* \return A pointer to a \c __DRIscreenPrivate on success, or \c NULL on
* failure.
*/
PUBLIC
void * __driCreateNewScreen_20050727( __DRInativeDisplay *dpy, int scrn, __DRIscreen *psc,
const __GLcontextModes * modes,
const __DRIversion * ddx_version,
const __DRIversion * dri_version,
const __DRIversion * drm_version,
const __DRIframebuffer * frame_buffer,
drmAddress pSAREA, int fd,
int internal_api_version,
const __DRIinterfaceMethods * interface,
__GLcontextModes ** driver_modes )
{
__DRIscreenPrivate *psp;
static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
static const __DRIversion dri_expected = { 4, 0, 0 };
static const __DRIversion drm_expected = { 1, 5, 0 };
dri_interface = interface;
if ( ! driCheckDriDdxDrmVersions3( "R200",
dri_version, & dri_expected,
ddx_version, & ddx_expected,
drm_version, & drm_expected ) ) {
return NULL;
}
psp = __driUtilCreateNewScreen(dpy, scrn, psc, NULL,
ddx_version, dri_version, drm_version,
frame_buffer, pSAREA, fd,
internal_api_version, &r200API);
if ( psp != NULL ) {
RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv;
*driver_modes = r200FillInModes( dri_priv->bpp,
(dri_priv->bpp == 16) ? 16 : 24,
(dri_priv->bpp == 16) ? 0 : 8,
(dri_priv->backOffset != dri_priv->depthOffset) );
/* Calling driInitExtensions here, with a NULL context pointer, does not actually
* enable the extensions. It just makes sure that all the dispatch offsets for all
* the extensions that *might* be enables are known. This is needed because the
* dispatch offsets need to be known when _mesa_context_create is called, but we can't
* enable the extensions until we have a context pointer.
*
* Hello chicken. Hello egg. How are you two today?
*/
driInitExtensions( NULL, card_extensions, GL_FALSE );
driInitExtensions( NULL, blend_extensions, GL_FALSE );
driInitSingleExtension( NULL, ARB_vp_extension );
driInitSingleExtension( NULL, NV_vp_extension );
driInitSingleExtension( NULL, ATI_fs_extension );
}
return (void *) psp;
}
/**
* Get information about previous buffer swaps.
*/
static int
getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo )
{
r200ContextPtr rmesa;
if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL)
|| (dPriv->driContextPriv->driverPrivate == NULL)
|| (sInfo == NULL) ) {
return -1;
}
rmesa = (r200ContextPtr) dPriv->driContextPriv->driverPrivate;
sInfo->swap_count = rmesa->swap_count;
sInfo->swap_ust = rmesa->swap_ust;
sInfo->swap_missed_count = rmesa->swap_missed_count;
sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0)
? driCalculateSwapUsage( dPriv, 0, rmesa->swap_missed_ust )
: 0.0;
return 0;
}

108
src/mesa/drivers/dri/r200/r200_screen.h
View file

@ -1,108 +0,0 @@
/* $XFree86: xc/lib/GL/mesa/src/drv/r200/r200_screen.h,v 1.1 2002/10/30 12:51:52 alanh Exp $ */
/*
Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
The Weather Channel (TM) funded Tungsten Graphics to develop the
initial release of the Radeon 8500 driver under the XFree86 license.
This notice must be preserved.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************/
/*
* Authors:
* Keith Whitwell <keith@tungstengraphics.com>
*/
#ifndef __R200_SCREEN_H__
#define __R200_SCREEN_H__
#include "xf86drm.h"
#include "drm.h"
#include "radeon_drm.h"
#include "dri_util.h"
#include "xmlconfig.h"
typedef struct {
drm_handle_t handle; /* Handle to the DRM region */
drmSize size; /* Size of the DRM region */
drmAddress map; /* Mapping of the DRM region */
} r200RegionRec, *r200RegionPtr;
/* chipset features */
#define R200_CHIPSET_TCL (1 << 0)
#define R200_CHIPSET_REAL_R200 (1 << 1)
#define R200_CHIPSET_YCBCR_BROKEN (1 << 2)
#define R200_NR_TEX_HEAPS 2
typedef struct {
int chipset;
int cpp;
int IsPCI; /* Current card is a PCI card */
int AGPMode;
unsigned int irq; /* IRQ number (0 means none) */
unsigned int fbLocation;
unsigned int frontOffset;
unsigned int frontPitch;
unsigned int backOffset;
unsigned int backPitch;
unsigned int depthOffset;
unsigned int depthPitch;
/* Shared texture data */
int numTexHeaps;
int texOffset[R200_NR_TEX_HEAPS];
int texSize[R200_NR_TEX_HEAPS];
int logTexGranularity[R200_NR_TEX_HEAPS];
r200RegionRec mmio;
r200RegionRec status;
r200RegionRec gartTextures;
drmBufMapPtr buffers;
__volatile__ u_int32_t *scratch; /* is this used for anything? */
__DRIscreenPrivate *driScreen;
unsigned int sarea_priv_offset;
unsigned int gart_buffer_offset; /* offset in card memory space */
unsigned int gart_texture_offset; /* offset in card memory space */
unsigned int gart_base;
GLboolean drmSupportsCubeMaps; /* need radeon kernel module >= 1.7 */
GLboolean drmSupportsBlendColor; /* need radeon kernel module >= 1.11 */
GLboolean drmSupportsTriPerf; /* need radeon kernel module >= 1.16 */
GLboolean drmSupportsFragShader; /* need radeon kernel module >= 1.18 */
GLboolean drmSupportsPointSprites; /* need radeon kernel module >= 1.13 */
GLboolean depthHasSurface;
/* Configuration cache with default values for all contexts */
driOptionCache optionCache;
} r200ScreenRec, *r200ScreenPtr;
#endif /* __R200_SCREEN_H__ */

2
src/mesa/drivers/dri/r200/r200_span.c
View file

@ -284,7 +284,7 @@ void r200InitSpanFuncs( GLcontext *ctx )
* Plug in the Get/Put routines for the given driRenderbuffer.
*/
void
r200SetSpanFunctions(driRenderbuffer *drb, const GLvisual *vis)
radeonSetSpanFunctions(driRenderbuffer *drb, const GLvisual *vis)
{
if (drb->Base.InternalFormat == GL_RGBA) {
if (vis->redBits == 5 && vis->greenBits == 6 && vis->blueBits == 5) {

2
src/mesa/drivers/dri/r200/r200_span.h
View file

@ -41,6 +41,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
extern void r200InitSpanFuncs( GLcontext *ctx );
extern void
r200SetSpanFunctions(driRenderbuffer *rb, const GLvisual *vis);
radeonSetSpanFunctions(driRenderbuffer *rb, const GLvisual *vis);
#endif

8
src/mesa/drivers/dri/r200/r200_state_init.c
View file

@ -253,7 +253,7 @@ void r200InitState( r200ContextPtr rmesa )
ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 );
ALLOC_STATE( tf, tf, TF_STATE_SIZE, "TF/tfactor", 0 );
if (rmesa->r200Screen->drmSupportsFragShader) {
if (rmesa->r200Screen->chipset & R200_CHIPSET_REAL_R200) {
if (rmesa->r200Screen->chip_family == CHIP_FAMILY_R200) {
/* make sure texture units 0/1 are emitted pair-wise for r200 t0 hang workaround */
ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE_NEWDRM, "TEX/tex-0", 0 );
ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE_NEWDRM, "TEX/tex-1", 1 );
@ -273,7 +273,7 @@ void r200InitState( r200ContextPtr rmesa )
ALLOC_STATE( afs[1], afs, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
}
else {
if (rmesa->r200Screen->chipset & R200_CHIPSET_REAL_R200) {
if (rmesa->r200Screen->chip_family == CHIP_FAMILY_R200) {
ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE_OLDDRM, "TEX/tex-0", 0 );
ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE_OLDDRM, "TEX/tex-1", 1 );
ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 );
@ -536,7 +536,7 @@ void r200InitState( r200ContextPtr rmesa )
if (rmesa->using_hyperz) {
rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_COMPRESSION_ENABLE |
R200_Z_DECOMPRESSION_ENABLE;
/* if (rmesa->r200Screen->chipset & R200_CHIPSET_REAL_R200)
/* if (rmesa->r200Screen->chip_family == CHIP_FAMILY_R200)
rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
}
@ -640,7 +640,7 @@ void r200InitState( r200ContextPtr rmesa )
R200_VC_NO_SWAP;
#endif
if (!(rmesa->r200Screen->chipset & R200_CHIPSET_TCL)) {
if (!(rmesa->r200Screen->chip_flags & RADEON_CHIPSET_TCL)) {
/* Bypass TCL */
rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] |= (1<<8);
}

2
src/mesa/drivers/dri/r200/r200_texstate.c
View file

@ -1678,7 +1678,7 @@ void r200UpdateTextureState( GLcontext *ctx )
r200ChooseVertexState( ctx );
if (rmesa->r200Screen->chipset & R200_CHIPSET_REAL_R200) {
if (rmesa->r200Screen->chip_family == CHIP_FAMILY_R200) {
/*
* T0 hang workaround -------------

12
src/mesa/drivers/dri/r300/Makefile
View file

@ -65,6 +65,8 @@ C_SOURCES = $(COMMON_SOURCES) $(DRIVER_SOURCES)
X86_SOURCES =
#r200_vtxtmp_x86.S
DEFINES += -DRADEON_COMMON=1 -DRADEON_COMMON_FOR_R300
SYMLINKS = \
server/radeon_dri.c \
server/radeon_dri.h \
@ -73,6 +75,11 @@ SYMLINKS = \
server/radeon_reg.h \
server/radeon_egl.c
COMMON_SYMLINKS = \
radeon_chipset.h \
radeon_screen.c \
radeon_screen.h
##### TARGETS #####
@ -82,5 +89,8 @@ $(SYMLINKS):
mkdir -p server
for i in $(SYMLINKS) ; do rm -f $$i && test -f ../radeon/$$i && ln -s ../../radeon/$$i $$i ; done
symlinks: $(SYMLINKS)
$(COMMON_SYMLINKS):
@[ -e $@ ] || ln -sf ../radeon/$@ ./
symlinks: $(SYMLINKS) $(COMMON_SYMLINKS)

2
src/mesa/drivers/dri/r300/r200_context.h
View file

@ -766,7 +766,7 @@ struct r200_context {
/* Texture object bookkeeping
*/
unsigned nr_heaps;
driTexHeap *texture_heaps[R200_NR_TEX_HEAPS];
driTexHeap *texture_heaps[RADEON_NR_TEX_HEAPS];
driTextureObject swapped;
int texture_depth;
float initialMaxAnisotropy;

8
src/mesa/drivers/dri/r300/r300_context.c
View file

@ -218,7 +218,7 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual,
make_empty_list(&r300->swapped);
r300->nr_heaps = 1 /* screen->numTexHeaps */ ;
assert(r300->nr_heaps < R200_NR_TEX_HEAPS);
assert(r300->nr_heaps < RADEON_NR_TEX_HEAPS);
for (i = 0; i < r300->nr_heaps; i++) {
r300->texture_heaps[i] = driCreateTextureHeap(i, r300,
screen->
@ -355,9 +355,9 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual,
#endif
}
if (tcl_mode == DRI_CONF_TCL_SW ||
!(r300->radeon.radeonScreen->chipset & RADEON_CHIPSET_TCL)) {
if (r300->radeon.radeonScreen->chipset & RADEON_CHIPSET_TCL) {
r300->radeon.radeonScreen->chipset &= ~RADEON_CHIPSET_TCL;
!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
if (r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
r300->radeon.radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL;
fprintf(stderr, "Disabling HW TCL support\n");
}
TCL_FALLBACK(r300->radeon.glCtx, RADEON_TCL_FALLBACK_TCL_DISABLE, 1);

2
src/mesa/drivers/dri/r300/r300_context.h
View file

@ -831,7 +831,7 @@ struct r300_context {
/* Texture object bookkeeping
*/
unsigned nr_heaps;
driTexHeap *texture_heaps[R200_NR_TEX_HEAPS];
driTexHeap *texture_heaps[RADEON_NR_TEX_HEAPS];
driTextureObject swapped;
int texture_depth;
float initialMaxAnisotropy;

6
src/mesa/drivers/dri/r300/r300_state.c
View file

@ -1992,7 +1992,7 @@ void r300ResetHwState(r300ContextPtr r300)
r300->hw.unk2220.cmd[3] = r300PackFloat32(1.0);
r300->hw.unk2220.cmd[4] = r300PackFloat32(1.0);
if (GET_CHIP(r300->radeon.radeonScreen) == RADEON_CHIP_R300)
if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R300)
r300->hw.unk2288.cmd[1] = R300_2288_R300;
else
r300->hw.unk2288.cmd[1] = R300_2288_RV350;
@ -2014,11 +2014,11 @@ void r300ResetHwState(r300ContextPtr r300)
r300->hw.gb_misc.cmd[R300_GB_MISC_MSPOS_0] = 0x66666666;
r300->hw.gb_misc.cmd[R300_GB_MISC_MSPOS_1] = 0x06666666;
if (GET_CHIP(r300->radeon.radeonScreen) == RADEON_CHIP_R300)
if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R300)
r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] = R300_GB_TILE_ENABLE
| R300_GB_TILE_PIPE_COUNT_R300
| R300_GB_TILE_SIZE_16;
else if (GET_CHIP(r300->radeon.radeonScreen) == RADEON_CHIP_R420)
else if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R420)
r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] = R300_GB_TILE_ENABLE
| R300_GB_TILE_PIPE_COUNT_R420
| R300_GB_TILE_SIZE_16;

6
src/mesa/drivers/dri/r300/radeon_context.c
View file

@ -78,7 +78,7 @@ static const GLubyte *radeonGetString(GLcontext * ctx, GLenum name)
radeon->radeonScreen->AGPMode;
const char* chipname;
if (IS_FAMILY_R300(radeon))
if (IS_R300_CLASS(radeon->radeonScreen))
chipname = "R300";
else
chipname = "R200";
@ -261,7 +261,7 @@ GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv,
radeon->dri.drawable = driDrawPriv;
#if R200_MERGED
if (IS_FAMILY_R200(radeon)) {
if (IS_R200_CLASS(radeon->radeonScreen)) {
r200UpdateWindow(radeon->glCtx);
r200UpdateViewportOffset(radeon->glCtx);
}
@ -282,7 +282,7 @@ GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv,
_mesa_update_state(radeon->glCtx);
#if R200_MERGED
if (IS_FAMILY_R200(radeon))
if (IS_R200_CLASS(radeon->radeonScreen))
r200ValidateState(radeon->glCtx);
#endif

12
src/mesa/drivers/dri/r300/radeon_ioctl.c
View file

@ -163,7 +163,7 @@ void radeonCopyBuffer(const __DRIdrawablePrivate * dPriv)
(void *)radeon->glCtx);
}
if (IS_FAMILY_R200(radeon))
if (IS_R200_CLASS(radeon->radeonScreen))
R200_FIREVERTICES((r200ContextPtr)radeon);
else
r300Flush(radeon->glCtx);
@ -205,7 +205,7 @@ void radeonCopyBuffer(const __DRIdrawablePrivate * dPriv)
UNLOCK_HARDWARE(radeon);
if (IS_FAMILY_R200(radeon))
if (IS_R200_CLASS(radeon->radeonScreen))
((r200ContextPtr)radeon)->hw.all_dirty = GL_TRUE;
else
((r300ContextPtr)radeon)->hw.all_dirty = GL_TRUE;
@ -239,7 +239,7 @@ void radeonPageFlip(const __DRIdrawablePrivate * dPriv)
radeon->sarea->pfCurrentPage);
}
if (IS_FAMILY_R200(radeon))
if (IS_R200_CLASS(radeon->radeonScreen))
R200_FIREVERTICES((r200ContextPtr)radeon);
else
r300Flush(radeon->glCtx);
@ -296,7 +296,7 @@ void radeonPageFlip(const __DRIdrawablePrivate * dPriv)
radeon->state.color.drawPitch = radeon->radeonScreen->backPitch;
}
if (IS_FAMILY_R200(radeon)) {
if (IS_R200_CLASS(radeon->radeonScreen)) {
r200ContextPtr r200 = (r200ContextPtr)radeon;
R200_STATECHANGE(r200, ctx);
@ -304,7 +304,7 @@ void radeonPageFlip(const __DRIdrawablePrivate * dPriv)
+ radeon->radeonScreen->fbLocation;
r200->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = radeon->state.color.drawPitch;
}
if (IS_FAMILY_R300(radeon)) {
if (IS_R300_CLASS(radeon->radeonScreen)) {
r300ContextPtr r300 = (r300ContextPtr)radeon;
R300_STATECHANGE(r300, cb);
r300->hw.cb.cmd[R300_CB_OFFSET] = r300->radeon.state.color.drawOffset +
@ -350,7 +350,7 @@ void radeonFlush(GLcontext * ctx)
{
radeonContextPtr radeon = RADEON_CONTEXT(ctx);
if (IS_FAMILY_R300(radeon))
if (IS_R300_CLASS(radeon->radeonScreen))
r300Flush(ctx);
#if R200_MERGED
else

2
src/mesa/drivers/dri/r300/radeon_lock.c
View file

@ -163,7 +163,7 @@ void radeonGetLock(radeonContextPtr radeon, GLuint flags)
if (sarea->ctx_owner != radeon->dri.hwContext)
sarea->ctx_owner = radeon->dri.hwContext;
if (IS_FAMILY_R300(radeon))
if (IS_R300_CLASS(radeon->radeonScreen))
r300RegainedLock(radeon);
#if R200_MERGED
else

2
src/mesa/drivers/dri/r300/radeon_lock.h
View file

@ -103,7 +103,7 @@ extern int prevLockLine;
(radeon)->dri.hwLock, \
(radeon)->dri.hwContext ); \
DEBUG_RESET(); \
if (IS_FAMILY_R200((radeon))) { \
if (IS_R200_CLASS(radeon->radeonScreen)) { \
r200ContextPtr __r200 = (r200ContextPtr)(radeon); \
if (__r200->save_on_next_unlock) \
r200SaveHwState( __r200 ); \

900
src/mesa/drivers/dri/r300/radeon_screen.c
View file

@ -1,900 +0,0 @@
/*
Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
The Weather Channel (TM) funded Tungsten Graphics to develop the
initial release of the Radeon 8500 driver under the XFree86 license.
This notice must be preserved.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************/
/**
* \file radeon_screen.c
* Screen initialization functions for the R200 driver.
*
* \author Keith Whitwell <keith@tungstengraphics.com>
*/
#include <dlfcn.h>
#include "glheader.h"
#include "imports.h"
#include "context.h"
#include "mtypes.h"
#include "framebuffer.h"
#include "renderbuffer.h"
#define STANDALONE_MMIO
#include "radeon_screen.h"
#include "r200_context.h"
#include "r300_context.h"
#include "radeon_ioctl.h"
#include "r200_ioctl.h"
#include "radeon_macros.h"
#include "radeon_reg.h"
#include "radeon_span.h"
#include "utils.h"
#include "vblank.h"
#include "GL/internal/dri_interface.h"
#include "drirenderbuffer.h"
/* R200 configuration
*/
#include "xmlpool.h"
const char __driR200ConfigOptions[] =
DRI_CONF_BEGIN
DRI_CONF_SECTION_PERFORMANCE
DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
DRI_CONF_MAX_TEXTURE_UNITS(4, 2, 6)
DRI_CONF_SECTION_END
DRI_CONF_SECTION_QUALITY
DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
DRI_CONF_NO_NEG_LOD_BIAS(false)
DRI_CONF_FORCE_S3TC_ENABLE(false)
DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
DRI_CONF_SECTION_END
DRI_CONF_SECTION_DEBUG
DRI_CONF_NO_RAST(false)
DRI_CONF_SECTION_END
DRI_CONF_SECTION_SOFTWARE
DRI_CONF_ARB_VERTEX_PROGRAM(true)
DRI_CONF_NV_VERTEX_PROGRAM(false)
DRI_CONF_SECTION_END
DRI_CONF_END;
static const GLuint __driR200NConfigOptions = 14;
/* TODO: integrate these into xmlpool.h! */
#define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
DRI_CONF_DESC(en,"Number of texture image units") \
DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
DRI_CONF_OPT_END
#define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
DRI_CONF_DESC(en,"Number of texture coordinate units") \
DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
DRI_CONF_OPT_END
#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
DRI_CONF_OPT_END
const char __driR300ConfigOptions[] =
DRI_CONF_BEGIN
DRI_CONF_SECTION_PERFORMANCE
DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(16, 2, 16)
DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
DRI_CONF_SECTION_END
DRI_CONF_SECTION_QUALITY
DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
DRI_CONF_NO_NEG_LOD_BIAS(false)
DRI_CONF_FORCE_S3TC_ENABLE(false)
DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
DRI_CONF_SECTION_END
DRI_CONF_SECTION_DEBUG
DRI_CONF_NO_RAST(false)
DRI_CONF_SECTION_END
DRI_CONF_END;
static const GLuint __driR300NConfigOptions = 14;
extern const struct dri_extension card_extensions[];
#ifndef RADEON_DEBUG
int RADEON_DEBUG = 0;
#endif
static const struct dri_debug_control debug_control[] = {
{"fall", DEBUG_FALLBACKS},
{"tex", DEBUG_TEXTURE},
{"ioctl", DEBUG_IOCTL},
{"prim", DEBUG_PRIMS},
{"vert", DEBUG_VERTS},
{"state", DEBUG_STATE},
{"code", DEBUG_CODEGEN},
{"vfmt", DEBUG_VFMT},
{"vtxf", DEBUG_VFMT},
{"verb", DEBUG_VERBOSE},
{"dri", DEBUG_DRI},
{"dma", DEBUG_DMA},
{"san", DEBUG_SANITY},
{"sync", DEBUG_SYNC},
{"pix", DEBUG_PIXEL},
{"mem", DEBUG_MEMORY},
{"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */
{NULL, 0}
};
#if 1
/* Including xf86PciInfo.h introduces a bunch of errors...
*/
#define PCI_CHIP_R200_QD 0x5144 /* why do they have r200 names? */
#define PCI_CHIP_R200_QE 0x5145 /* Those are all standard radeons */
#define PCI_CHIP_R200_QF 0x5146
#define PCI_CHIP_R200_QG 0x5147
#define PCI_CHIP_R200_QY 0x5159
#define PCI_CHIP_R200_QZ 0x515A
#define PCI_CHIP_R200_LW 0x4C57
#define PCI_CHIP_R200_LY 0x4C59
#define PCI_CHIP_R200_LZ 0x4C5A
#define PCI_CHIP_RV200_QW 0x5157 /* Radeon 7500 - not an R200 at all */
#define PCI_CHIP_RV200_QX 0x5158
#define PCI_CHIP_RS100_4136 0x4136 /* IGP RS100, RS200, RS250 are not R200 */
#define PCI_CHIP_RS200_4137 0x4137
#define PCI_CHIP_RS250_4237 0x4237
#define PCI_CHIP_RS100_4336 0x4336
#define PCI_CHIP_RS200_4337 0x4337
#define PCI_CHIP_RS250_4437 0x4437
#define PCI_CHIP_RS300_5834 0x5834 /* All RS300's are R200 */
#define PCI_CHIP_RS300_5835 0x5835
#define PCI_CHIP_RS300_5836 0x5836
#define PCI_CHIP_RS300_5837 0x5837
#define PCI_CHIP_R200_BB 0x4242 /* r200 (non-derived) start */
#define PCI_CHIP_R200_BC 0x4243
#define PCI_CHIP_R200_QH 0x5148
#define PCI_CHIP_R200_QI 0x5149
#define PCI_CHIP_R200_QJ 0x514A
#define PCI_CHIP_R200_QK 0x514B
#define PCI_CHIP_R200_QL 0x514C
#define PCI_CHIP_R200_QM 0x514D
#define PCI_CHIP_R200_QN 0x514E
#define PCI_CHIP_R200_QO 0x514F /* r200 (non-derived) end */
/* are the R200 Qh (0x5168) and following needed too? They are not in xf86PciInfo.h
but in the pci database. Maybe just secondary ports or something ? */
#define PCI_CHIP_R300_AD 0x4144
#define PCI_CHIP_R300_AE 0x4145
#define PCI_CHIP_R300_AF 0x4146
#define PCI_CHIP_R300_AG 0x4147
#define PCI_CHIP_RV350_AP 0x4150
#define PCI_CHIP_RV350_AQ 0x4151
#define PCI_CHIP_RV350_AR 0x4152
#define PCI_CHIP_RV350_AS 0x4153
#define PCI_CHIP_RV350_NJ 0x4E4A
#define PCI_CHIP_RV350_NP 0x4E50
#define PCI_CHIP_RV350_NQ 0x4E51 /* Saphire 9600 256MB card */
#define PCI_CHIP_RV350_NT 0x4E54
#define PCI_CHIP_RV350_NQ_2 0x4E71 /* Saphire 9600 256MB card - Second Head */
#define PCI_CHIP_R300_ND 0x4E44
#define PCI_CHIP_R300_NE 0x4E45
#define PCI_CHIP_R300_NF 0x4E46
#define PCI_CHIP_R300_NG 0x4E47
#define PCI_CHIP_R350_NH 0x4E48
#define PCI_CHIP_R420_JI 0x4A49
#define PCI_CHIP_R420_JK 0x4a4b
#define PCI_CHIP_RV370_5460 0x5460
#endif
static radeonScreenPtr __radeonScreen;
static int getSwapInfo(__DRIdrawablePrivate * dPriv, __DRIswapInfo * sInfo);
static __GLcontextModes *radeonFillInModes(unsigned pixel_bits,
unsigned depth_bits,
unsigned stencil_bits,
GLboolean have_back_buffer)
{
__GLcontextModes *modes;
__GLcontextModes *m;
unsigned num_modes;
unsigned depth_buffer_factor;
unsigned back_buffer_factor;
GLenum fb_format;
GLenum fb_type;
/* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
* enough to add support. Basically, if a context is created with an
* fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
* will never be used.
*/
static const GLenum back_buffer_modes[] = {
GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
};
uint8_t depth_bits_array[2];
uint8_t stencil_bits_array[2];
depth_bits_array[0] = depth_bits;
depth_bits_array[1] = depth_bits;
/* Just like with the accumulation buffer, always provide some modes
* with a stencil buffer. It will be a sw fallback, but some apps won't
* care about that.
*/
stencil_bits_array[0] = 0;
stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits;
depth_buffer_factor = ((depth_bits != 0)
|| (stencil_bits != 0)) ? 2 : 1;
back_buffer_factor = (have_back_buffer) ? 2 : 1;
num_modes = depth_buffer_factor * back_buffer_factor * 4;
if (pixel_bits == 16) {
fb_format = GL_RGB;
fb_type = GL_UNSIGNED_SHORT_5_6_5;
} else {
fb_format = GL_BGRA;
fb_type = GL_UNSIGNED_INT_8_8_8_8_REV;
}
modes = (*dri_interface->createContextModes) (num_modes, sizeof(__GLcontextModes));
m = modes;
if (!driFillInModes(&m, fb_format, fb_type,
depth_bits_array, stencil_bits_array,
depth_buffer_factor, back_buffer_modes,
back_buffer_factor, GLX_TRUE_COLOR)) {
fprintf(stderr, "[%s:%u] Error creating FBConfig!\n", __func__,
__LINE__);
return NULL;
}
if (!driFillInModes(&m, fb_format, fb_type,
depth_bits_array, stencil_bits_array,
depth_buffer_factor, back_buffer_modes,
back_buffer_factor, GLX_DIRECT_COLOR)) {
fprintf(stderr, "[%s:%u] Error creating FBConfig!\n", __func__,
__LINE__);
return NULL;
}
/* Mark the visual as slow if there are "fake" stencil bits.
*/
for (m = modes; m != NULL; m = m->next) {
if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) {
m->visualRating = GLX_SLOW_CONFIG;
}
}
return modes;
}
/* Create the device specific screen private data struct.
*/
static radeonScreenPtr radeonCreateScreen(__DRIscreenPrivate * sPriv)
{
radeonScreenPtr screen;
RADEONDRIPtr dri_priv = (RADEONDRIPtr) sPriv->pDevPriv;
unsigned char *RADEONMMIO;
PFNGLXSCRENABLEEXTENSIONPROC glx_enable_extension =
(PFNGLXSCRENABLEEXTENSIONPROC)
(*dri_interface->getProcAddress("glxEnableExtension"));
void *const psc = sPriv->psc->screenConfigs;
if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) {
fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n");
return GL_FALSE;
}
/* Allocate the private area */
screen = (radeonScreenPtr) CALLOC(sizeof(*screen));
if (!screen) {
__driUtilMessage
("%s: Could not allocate memory for screen structure",
__FUNCTION__);
return NULL;
}
#if DO_DEBUG
RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control);
#endif
/* Get family and potential quirks from the PCI device ID.
*/
switch (dri_priv->deviceID) {
case PCI_CHIP_R200_QD:
case PCI_CHIP_R200_QE:
case PCI_CHIP_R200_QF:
case PCI_CHIP_R200_QG:
case PCI_CHIP_R200_QY:
case PCI_CHIP_R200_QZ:
case PCI_CHIP_RV200_QW:
case PCI_CHIP_RV200_QX:
case PCI_CHIP_R200_LW:
case PCI_CHIP_R200_LY:
case PCI_CHIP_R200_LZ:
case PCI_CHIP_RS100_4136:
case PCI_CHIP_RS200_4137:
case PCI_CHIP_RS250_4237:
case PCI_CHIP_RS100_4336:
case PCI_CHIP_RS200_4337:
case PCI_CHIP_RS250_4437:
__driUtilMessage("radeonCreateScreen(): Device isn't an r200!\n");
FREE(screen);
return NULL;
case PCI_CHIP_RS300_5834:
case PCI_CHIP_RS300_5835:
case PCI_CHIP_RS300_5836:
case PCI_CHIP_RS300_5837:
screen->chipset = RADEON_CHIP_UNREAL_R200;
break;
case PCI_CHIP_R200_BB:
case PCI_CHIP_R200_BC:
case PCI_CHIP_R200_QH:
case PCI_CHIP_R200_QI:
case PCI_CHIP_R200_QJ:
case PCI_CHIP_R200_QK:
case PCI_CHIP_R200_QL:
case PCI_CHIP_R200_QM:
case PCI_CHIP_R200_QN:
case PCI_CHIP_R200_QO:
screen->chipset = RADEON_CHIP_REAL_R200 | RADEON_CHIPSET_TCL;
break;
/* TODO: Check all those chips for the exact flags required.
*/
case PCI_CHIP_R300_AD:
case PCI_CHIP_R300_AE:
case PCI_CHIP_R300_AF:
case PCI_CHIP_R300_AG:
case PCI_CHIP_RV350_AP:
case PCI_CHIP_RV350_AQ:
case PCI_CHIP_RV350_AR:
case PCI_CHIP_RV350_AS:
case PCI_CHIP_RV350_NJ:
case PCI_CHIP_RV350_NP:
case PCI_CHIP_RV350_NT:
case PCI_CHIP_RV350_NQ:
/* case PCI_CHIP_RV350_NQ: -- Should we have the second head in here too? */
case PCI_CHIP_RV370_5460:
screen->chipset = RADEON_CHIP_RV350;
break;
case PCI_CHIP_R300_ND: /* confirmed -- nh */
case PCI_CHIP_R300_NE:
case PCI_CHIP_R300_NF:
case PCI_CHIP_R300_NG:
case PCI_CHIP_R350_NH:
screen->chipset = RADEON_CHIP_R300;
break;
case PCI_CHIP_R420_JI:
case PCI_CHIP_R420_JK:
screen->chipset = RADEON_CHIP_R420;
break;
default:
fprintf(stderr,
"Unknown device ID %04X, please report. Assuming plain R300.\n",
dri_priv->deviceID);
screen->chipset = RADEON_CHIP_R300;
}
/* Parse configuration */
if (GET_CHIP(screen) >= RADEON_CHIP_R300) {
driParseOptionInfo(&screen->optionCache,
__driR300ConfigOptions, __driR300NConfigOptions);
} else {
driParseOptionInfo(&screen->optionCache,
__driR200ConfigOptions, __driR200NConfigOptions);
}
/* This is first since which regions we map depends on whether or
* not we are using a PCI card.
*/
screen->IsPCI = dri_priv->IsPCI;
{
int ret;
drm_radeon_getparam_t gp;
gp.param = RADEON_PARAM_GART_BUFFER_OFFSET;
gp.value = &screen->gart_buffer_offset;
ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_GETPARAM,
&gp, sizeof(gp));
if (ret) {
FREE(screen);
fprintf(stderr,
"drmRadeonGetParam (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n",
ret);
return NULL;
}
if (sPriv->drmMinor >= 6) {
gp.param = RADEON_PARAM_GART_BASE;
gp.value = &screen->gart_base;
ret =
drmCommandWriteRead(sPriv->fd, DRM_RADEON_GETPARAM,
&gp, sizeof(gp));
if (ret) {
FREE(screen);
fprintf(stderr,
"drmR200GetParam (RADEON_PARAM_GART_BASE): %d\n",
ret);
return NULL;
}
gp.param = RADEON_PARAM_IRQ_NR;
gp.value = &screen->irq;
ret =
drmCommandWriteRead(sPriv->fd, DRM_RADEON_GETPARAM,
&gp, sizeof(gp));
if (ret) {
FREE(screen);
fprintf(stderr,
"drmRadeonGetParam (RADEON_PARAM_IRQ_NR): %d\n",
ret);
return NULL;
}
/* Check if kernel module is new enough to support cube maps */
screen->drmSupportsCubeMaps = (sPriv->drmMinor >= 7);
/* Check if kernel module is new enough to support blend color and
separate blend functions/equations */
screen->drmSupportsBlendColor = (sPriv->drmMinor >= 11);
}
}
screen->mmio.handle = dri_priv->registerHandle;
screen->mmio.size = dri_priv->registerSize;
if (drmMap(sPriv->fd,
screen->mmio.handle, screen->mmio.size, &screen->mmio.map)) {
FREE(screen);
__driUtilMessage("%s: drmMap failed\n", __FUNCTION__);
return NULL;
}
RADEONMMIO = screen->mmio.map;
screen->status.handle = dri_priv->statusHandle;
screen->status.size = dri_priv->statusSize;
if (drmMap(sPriv->fd,
screen->status.handle,
screen->status.size, &screen->status.map)) {
drmUnmap(screen->mmio.map, screen->mmio.size);
FREE(screen);
__driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__);
return NULL;
}
screen->scratch = (__volatile__ uint32_t *)
((GLubyte *) screen->status.map + RADEON_SCRATCH_REG_OFFSET);
screen->buffers = drmMapBufs(sPriv->fd);
if (!screen->buffers) {
drmUnmap(screen->status.map, screen->status.size);
drmUnmap(screen->mmio.map, screen->mmio.size);
FREE(screen);
__driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__);
return NULL;
}
if (dri_priv->gartTexHandle && dri_priv->gartTexMapSize) {
screen->gartTextures.handle = dri_priv->gartTexHandle;
screen->gartTextures.size = dri_priv->gartTexMapSize;
if (drmMap(sPriv->fd,
screen->gartTextures.handle,
screen->gartTextures.size,
(drmAddressPtr) & screen->gartTextures.map)) {
drmUnmapBufs(screen->buffers);
drmUnmap(screen->status.map, screen->status.size);
drmUnmap(screen->mmio.map, screen->mmio.size);
FREE(screen);
__driUtilMessage
("%s: drmMAP failed for GART texture area\n",
__FUNCTION__);
return NULL;
}
screen->gart_texture_offset =
dri_priv->gartTexOffset +
(screen->IsPCI ? INREG(RADEON_AIC_LO_ADDR)
: ((INREG(RADEON_MC_AGP_LOCATION) & 0x0ffffU) << 16));
}
screen->cpp = dri_priv->bpp / 8;
screen->AGPMode = dri_priv->AGPMode;
screen->fbLocation = (INREG(RADEON_MC_FB_LOCATION) & 0xffff) << 16;
if (sPriv->drmMinor >= 10) {
drm_radeon_setparam_t sp;
sp.param = RADEON_SETPARAM_FB_LOCATION;
sp.value = screen->fbLocation;
drmCommandWrite(sPriv->fd, DRM_RADEON_SETPARAM,
&sp, sizeof(sp));
}
screen->frontOffset = dri_priv->frontOffset;
screen->frontPitch = dri_priv->frontPitch;
screen->backOffset = dri_priv->backOffset;
screen->backPitch = dri_priv->backPitch;
screen->depthOffset = dri_priv->depthOffset;
screen->depthPitch = dri_priv->depthPitch;
/* Check if ddx has set up a surface reg to cover depth buffer */
screen->depthHasSurface = (sPriv->ddxMajor > 4);
screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
+ screen->fbLocation;
screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
dri_priv->log2TexGran;
if (!screen->gartTextures.map) {
screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1;
screen->texOffset[RADEON_GART_TEX_HEAP] = 0;
screen->texSize[RADEON_GART_TEX_HEAP] = 0;
screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0;
} else {
screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
screen->texOffset[RADEON_GART_TEX_HEAP] =
screen->gart_texture_offset;
screen->texSize[RADEON_GART_TEX_HEAP] =
dri_priv->gartTexMapSize;
screen->logTexGranularity[RADEON_GART_TEX_HEAP] =
dri_priv->log2GARTTexGran;
}
screen->driScreen = sPriv;
screen->sarea_priv_offset = dri_priv->sarea_priv_offset;
if (glx_enable_extension != NULL) {
if (screen->irq != 0) {
(*glx_enable_extension) (psc, "GLX_SGI_swap_control");
(*glx_enable_extension) (psc, "GLX_SGI_video_sync");
(*glx_enable_extension) (psc, "GLX_MESA_swap_control");
}
(*glx_enable_extension) (psc, "GLX_MESA_swap_frame_usage");
}
#if R200_MERGED
sPriv->psc->allocateMemory = (void *)r200AllocateMemoryMESA;
sPriv->psc->freeMemory = (void *)r200FreeMemoryMESA;
sPriv->psc->memoryOffset = (void *)r200GetMemoryOffsetMESA;
if (glx_enable_extension != NULL) {
(*glx_enable_extension) (psc, "GLX_MESA_allocate_memory");
}
#endif
return screen;
}
/* Destroy the device specific screen private data struct.
*/
static void radeonDestroyScreen(__DRIscreenPrivate * sPriv)
{
radeonScreenPtr screen = (radeonScreenPtr) sPriv->private;
if (!screen)
return;
if (screen->gartTextures.map) {
drmUnmap(screen->gartTextures.map, screen->gartTextures.size);
}
drmUnmapBufs(screen->buffers);
drmUnmap(screen->status.map, screen->status.size);
drmUnmap(screen->mmio.map, screen->mmio.size);
/* free all option information */
driDestroyOptionInfo(&screen->optionCache);
FREE(screen);
sPriv->private = NULL;
}
/* Initialize the driver specific screen private data.
*/
static GLboolean radeonInitDriver(__DRIscreenPrivate * sPriv)
{
__radeonScreen = radeonCreateScreen(sPriv);
sPriv->private = (void *)__radeonScreen;
return sPriv->private ? GL_TRUE : GL_FALSE;
}
/**
* Create and initialize the Mesa and driver specific pixmap buffer
* data.
*
* \todo This function (and its interface) will need to be updated to support
* pbuffers.
*/
static GLboolean
radeonCreateBuffer(__DRIscreenPrivate * driScrnPriv,
__DRIdrawablePrivate * driDrawPriv,
const __GLcontextModes * mesaVis, GLboolean isPixmap)
{
radeonScreenPtr screen = (radeonScreenPtr)driScrnPriv->private;
if (isPixmap) {
return GL_FALSE; /* not implemented */
} else {
const GLboolean swDepth = GL_FALSE;
const GLboolean swAlpha = GL_FALSE;
const GLboolean swAccum = mesaVis->accumRedBits > 0;
const GLboolean swStencil = mesaVis->stencilBits > 0 &&
mesaVis->depthBits != 24;
struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis);
{
driRenderbuffer *frontRb
= driNewRenderbuffer(GL_RGBA,
driScrnPriv->pFB + screen->frontOffset,
screen->cpp,
screen->frontOffset,
screen->frontPitch,
driDrawPriv);
radeonSetSpanFunctions(frontRb, mesaVis);
_mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &frontRb->Base);
}
if (mesaVis->doubleBufferMode) {
driRenderbuffer *backRb
= driNewRenderbuffer(GL_RGBA,
driScrnPriv->pFB + screen->backOffset,
screen->cpp,
screen->backOffset,
screen->backPitch,
driDrawPriv);
radeonSetSpanFunctions(backRb, mesaVis);
_mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &backRb->Base);
}
if (mesaVis->depthBits == 16) {
driRenderbuffer *depthRb
= driNewRenderbuffer(GL_DEPTH_COMPONENT16,
driScrnPriv->pFB + screen->depthOffset,
screen->cpp,
screen->depthOffset,
screen->depthPitch,
driDrawPriv);
radeonSetSpanFunctions(depthRb, mesaVis);
_mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
depthRb->depthHasSurface = screen->depthHasSurface;
}
else if (mesaVis->depthBits == 24) {
driRenderbuffer *depthRb
= driNewRenderbuffer(GL_DEPTH_COMPONENT24,
driScrnPriv->pFB + screen->depthOffset,
screen->cpp,
screen->depthOffset,
screen->depthPitch,
driDrawPriv);
radeonSetSpanFunctions(depthRb, mesaVis);
_mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
depthRb->depthHasSurface = screen->depthHasSurface;
}
if (mesaVis->stencilBits > 0 && !swStencil) {
driRenderbuffer *stencilRb
= driNewRenderbuffer(GL_STENCIL_INDEX8_EXT,
driScrnPriv->pFB + screen->depthOffset,
screen->cpp,
screen->depthOffset,
screen->depthPitch,
driDrawPriv);
radeonSetSpanFunctions(stencilRb, mesaVis);
_mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencilRb->Base);
stencilRb->depthHasSurface = screen->depthHasSurface;
}
_mesa_add_soft_renderbuffers(fb,
GL_FALSE, /* color */
swDepth,
swStencil,
swAccum,
swAlpha,
GL_FALSE /* aux */);
driDrawPriv->driverPrivate = (void *) fb;
return (driDrawPriv->driverPrivate != NULL);
}
}
static void radeonDestroyBuffer(__DRIdrawablePrivate * driDrawPriv)
{
_mesa_destroy_framebuffer((GLframebuffer *) (driDrawPriv->
driverPrivate));
}
/**
* Choose the appropriate CreateContext function based on the chipset.
*/
static GLboolean radeonCreateContext(const __GLcontextModes * glVisual,
__DRIcontextPrivate * driContextPriv,
void *sharedContextPriv)
{
__DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
int chip = GET_CHIP(screen);
if (chip >= RADEON_CHIP_R300)
return r300CreateContext(glVisual, driContextPriv, sharedContextPriv);
#if R200_MERGED
else
return r200CreateContext(glVisual, driContextPriv, sharedContextPriv);
#endif
return GL_FALSE;
}
/**
* Choose the appropriate DestroyContext function based on the chipset.
*/
static void radeonDestroyContext(__DRIcontextPrivate * driContextPriv)
{
radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate;
int chip = GET_CHIP(radeon->radeonScreen);
if (chip >= RADEON_CHIP_R300)
return r300DestroyContext(driContextPriv);
#if R200_MERGED
else
return r200DestroyContext(driContextPriv);
#endif
}
static const struct __DriverAPIRec radeonAPI = {
.InitDriver = radeonInitDriver,
.DestroyScreen = radeonDestroyScreen,
.CreateContext = radeonCreateContext,
.DestroyContext = radeonDestroyContext,
.CreateBuffer = radeonCreateBuffer,
.DestroyBuffer = radeonDestroyBuffer,
.SwapBuffers = radeonSwapBuffers,
.MakeCurrent = radeonMakeCurrent,
.UnbindContext = radeonUnbindContext,
.GetSwapInfo = getSwapInfo,
.GetMSC = driGetMSC32,
.WaitForMSC = driWaitForMSC32,
.WaitForSBC = NULL,
.SwapBuffersMSC = NULL
};
/**
* This is the bootstrap function for the driver. libGL supplies all of the
* requisite information about the system, and the driver initializes itself.
* This routine also fills in the linked list pointed to by \c driver_modes
* with the \c __GLcontextModes that the driver can support for windows or
* pbuffers.
*
* \return A pointer to a \c __DRIscreenPrivate on success, or \c NULL on
* failure.
*/
void *__driCreateNewScreen_20050727(__DRInativeDisplay * dpy, int scrn,
__DRIscreen * psc, const __GLcontextModes * modes,
const __DRIversion * ddx_version,
const __DRIversion * dri_version,
const __DRIversion * drm_version,
const __DRIframebuffer * frame_buffer,
drmAddress pSAREA, int fd, int internal_api_version,
const __DRIinterfaceMethods * interface,
__GLcontextModes ** driver_modes)
{
__DRIscreenPrivate *psp;
static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
static const __DRIversion dri_expected = { 4, 0, 0 };
static const __DRIversion drm_expected = { 1, 17, 0 };
dri_interface = interface;
if (!driCheckDriDdxDrmVersions3("R300",
dri_version, &dri_expected,
ddx_version, &ddx_expected,
drm_version, &drm_expected)) {
return NULL;
}
psp = __driUtilCreateNewScreen(dpy, scrn, psc, NULL,
ddx_version, dri_version, drm_version,
frame_buffer, pSAREA, fd,
internal_api_version, &radeonAPI);
if (psp != NULL) {
RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv;
*driver_modes = radeonFillInModes(dri_priv->bpp,
(dri_priv->bpp ==
16) ? 16 : 24,
(dri_priv->bpp ==
16) ? 0 : 8,
(dri_priv->backOffset !=
dri_priv->depthOffset));
/* Calling driInitExtensions here, with a NULL context pointer, does not actually
* enable the extensions. It just makes sure that all the dispatch offsets for all
* the extensions that *might* be enables are known. This is needed because the
* dispatch offsets need to be known when _mesa_context_create is called, but we can't
* enable the extensions until we have a context pointer.
*
* Hello chicken. Hello egg. How are you two today?
*/
driInitExtensions( NULL, card_extensions, GL_FALSE );
}
return (void *)psp;
}
/**
* Get information about previous buffer swaps.
*/
static int getSwapInfo(__DRIdrawablePrivate * dPriv, __DRIswapInfo * sInfo)
{
radeonContextPtr radeon;
if ((dPriv == NULL) || (dPriv->driContextPriv == NULL)
|| (dPriv->driContextPriv->driverPrivate == NULL)
|| (sInfo == NULL)) {
return -1;
}
radeon = (radeonContextPtr) dPriv->driContextPriv->driverPrivate;
sInfo->swap_count = radeon->swap_count;
sInfo->swap_ust = radeon->swap_ust;
sInfo->swap_missed_count = radeon->swap_missed_count;
sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0)
? driCalculateSwapUsage(dPriv, 0, radeon->swap_missed_ust)
: 0.0;
return 0;
}

113
src/mesa/drivers/dri/r300/radeon_screen.h
View file

@ -1,113 +0,0 @@
/*
Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
The Weather Channel (TM) funded Tungsten Graphics to develop the
initial release of the Radeon 8500 driver under the XFree86 license.
This notice must be preserved.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************/
/*
* Authors:
* Keith Whitwell <keith@tungstengraphics.com>
*/
#ifndef __RADEON_SCREEN_H__
#define __RADEON_SCREEN_H__
#ifdef GLX_DIRECT_RENDERING
#include "xf86drm.h"
#include "drm.h"
#include "radeon_drm.h"
#include "dri_util.h"
#include "xmlconfig.h"
typedef struct {
drm_handle_t handle; /* Handle to the DRM region */
drmSize size; /* Size of the DRM region */
drmAddress map; /* Mapping of the DRM region */
} radeonRegionRec, *radeonRegionPtr;
/* chipset features */
#define RADEON_CHIP_UNREAL_R200 0
#define RADEON_CHIP_REAL_R200 1
#define RADEON_CHIP_R300 2
#define RADEON_CHIP_RV350 3
#define RADEON_CHIP_R420 4
#define RADEON_CHIP_MASK 0x0f
#define RADEON_CHIPSET_TCL (1 << 8)
#define GET_CHIP(screen) ((screen)->chipset & RADEON_CHIP_MASK)
#define IS_FAMILY_R200(radeon) (GET_CHIP((radeon)->radeonScreen) < RADEON_CHIP_R300)
#define IS_FAMILY_R300(radeon) (GET_CHIP((radeon)->radeonScreen) >= RADEON_CHIP_R300)
#define R200_NR_TEX_HEAPS 2
typedef struct {
int chipset;
int cpp;
int IsPCI; /* Current card is a PCI card */
int AGPMode;
unsigned int irq; /* IRQ number (0 means none) */
unsigned int fbLocation;
unsigned int frontOffset;
unsigned int frontPitch;
unsigned int backOffset;
unsigned int backPitch;
unsigned int depthOffset;
unsigned int depthPitch;
/* Shared texture data */
int numTexHeaps;
int texOffset[R200_NR_TEX_HEAPS];
int texSize[R200_NR_TEX_HEAPS];
int logTexGranularity[R200_NR_TEX_HEAPS];
radeonRegionRec mmio;
radeonRegionRec status;
radeonRegionRec gartTextures;
drmBufMapPtr buffers;
__volatile__ uint32_t *scratch;
__DRIscreenPrivate *driScreen;
unsigned int sarea_priv_offset;
unsigned int gart_buffer_offset; /* offset in card memory space */
unsigned int gart_texture_offset; /* offset in card memory space */
unsigned int gart_base;
GLboolean drmSupportsCubeMaps; /* need radeon kernel module >=1.7 */
GLboolean drmSupportsBlendColor; /* need radeon kernel module >= 1.11 */
GLboolean depthHasSurface;
/* Configuration cache with default values for all contexts */
driOptionCache optionCache;
} radeonScreenRec, *radeonScreenPtr;
#endif
#endif /* __RADEON_SCREEN_H__ */

4
src/mesa/drivers/dri/r300/radeon_state.c
View file

@ -142,7 +142,7 @@ static void radeonScissor(GLcontext* ctx, GLint x, GLint y, GLsizei w, GLsizei h
if (ctx->Scissor.Enabled) {
/* We don't pipeline cliprect changes */
if (IS_FAMILY_R200(radeon))
if (IS_R200_CLASS(radeon->radeonScreen))
R200_FIREVERTICES((r200ContextPtr)radeon);
else
r300Flush(ctx);
@ -198,7 +198,7 @@ void radeonEnable(GLcontext* ctx, GLenum cap, GLboolean state)
switch(cap) {
case GL_SCISSOR_TEST:
/* We don't pipeline cliprect & scissor changes */
if (IS_FAMILY_R200(radeon))
if (IS_R200_CLASS(radeon->radeonScreen))
R200_FIREVERTICES((r200ContextPtr)radeon);
else
r300Flush(ctx);

1
src/mesa/drivers/dri/radeon/Makefile
View file

@ -32,6 +32,7 @@ C_SOURCES = \
$(COMMON_SOURCES) \
$(DRIVER_SOURCES)
DEFINES += -DRADEON_COMMON=0
X86_SOURCES = \
radeon_vtxtmp_x86.S

135
src/mesa/drivers/dri/radeon/radeon_chipset.h Normal file
View file

@ -0,0 +1,135 @@
#ifndef _RADEON_CHIPSET_H
#define _RADEON_CHIPSET_H
/* Including xf86PciInfo.h introduces a bunch of errors...
*/
/* General chip classes:
* r100 includes R100, RV100, RV200, RS100, RS200, RS250.
* r200 includes R200, RV250, RV280, RS300.
* r300 includes R300, RV350, RV370.
* (RS* denotes IGP)
*/
#define PCI_CHIP_RS100_4136 0x4136
#define PCI_CHIP_RS200_4137 0x4137
#define PCI_CHIP_R300_AD 0x4144
#define PCI_CHIP_R300_AE 0x4145
#define PCI_CHIP_R300_AF 0x4146
#define PCI_CHIP_R300_AG 0x4147
#define PCI_CHIP_R350_AH 0x4148
#define PCI_CHIP_R350_AI 0x4149
#define PCI_CHIP_R350_AJ 0x414A
#define PCI_CHIP_R350_AK 0x414B
#define PCI_CHIP_RV350_AP 0x4150
#define PCI_CHIP_RV350_AQ 0x4151
#define PCI_CHIP_RV350_AR 0x4152
#define PCI_CHIP_RV350_AS 0x4153
#define PCI_CHIP_RV350_AT 0x4154
#define PCI_CHIP_RV350_AU 0x4155
#define PCI_CHIP_RV350_AV 0x4156
#define PCI_CHIP_RS250_4237 0x4237
#define PCI_CHIP_R200_BB 0x4242
#define PCI_CHIP_R200_BC 0x4243
#define PCI_CHIP_RS100_4336 0x4336
#define PCI_CHIP_RS200_4337 0x4337
#define PCI_CHIP_RS250_4437 0x4437
#define PCI_CHIP_RV250_Id 0x4964
#define PCI_CHIP_RV250_Ie 0x4965
#define PCI_CHIP_RV250_If 0x4966
#define PCI_CHIP_RV250_Ig 0x4967
#define PCI_CHIP_R420_JH 0x4A48
#define PCI_CHIP_R420_JI 0x4A49
#define PCI_CHIP_R420_JJ 0x4A4A
#define PCI_CHIP_R420_JK 0x4A4B
#define PCI_CHIP_R420_JL 0x4A4C
#define PCI_CHIP_R420_JM 0x4A4D
#define PCI_CHIP_R420_JN 0x4A4E
#define PCI_CHIP_R420_JO 0x4A4F
#define PCI_CHIP_R420_JP 0x4A50
#define PCI_CHIP_RADEON_LW 0x4C57
#define PCI_CHIP_RADEON_LX 0x4C58
#define PCI_CHIP_RADEON_LY 0x4C59
#define PCI_CHIP_RADEON_LZ 0x4C5A
#define PCI_CHIP_RV250_Ld 0x4C64
#define PCI_CHIP_RV250_Le 0x4C65
#define PCI_CHIP_RV250_Lf 0x4C66
#define PCI_CHIP_RV250_Lg 0x4C67
#define PCI_CHIP_RV250_Ln 0x4C6E
#define PCI_CHIP_R300_ND 0x4E44
#define PCI_CHIP_R300_NE 0x4E45
#define PCI_CHIP_R300_NF 0x4E46
#define PCI_CHIP_R300_NG 0x4E47
#define PCI_CHIP_R350_NH 0x4E48
#define PCI_CHIP_R350_NI 0x4E49
#define PCI_CHIP_R360_NJ 0x4E4A
#define PCI_CHIP_R350_NK 0x4E4B
#define PCI_CHIP_RV350_NP 0x4E50
#define PCI_CHIP_RV350_NQ 0x4E51
#define PCI_CHIP_RV350_NR 0x4E52
#define PCI_CHIP_RV350_NS 0x4E53
#define PCI_CHIP_RV350_NT 0x4E54
#define PCI_CHIP_RV350_NV 0x4E56
#define PCI_CHIP_RADEON_QD 0x5144
#define PCI_CHIP_RADEON_QE 0x5145
#define PCI_CHIP_RADEON_QF 0x5146
#define PCI_CHIP_RADEON_QG 0x5147
#define PCI_CHIP_RADEON_QY 0x5159
#define PCI_CHIP_RADEON_QZ 0x515A
#define PCI_CHIP_RN50_515E 0x515E
#define PCI_CHIP_R200_QH 0x5148
#define PCI_CHIP_R200_QI 0x5149
#define PCI_CHIP_R200_QJ 0x514A
#define PCI_CHIP_R200_QK 0x514B
#define PCI_CHIP_R200_QL 0x514C
#define PCI_CHIP_R200_QM 0x514D
#define PCI_CHIP_R200_QN 0x514E
#define PCI_CHIP_R200_QO 0x514F
#define PCI_CHIP_RV200_QW 0x5157
#define PCI_CHIP_RV200_QX 0x5158
#define PCI_CHIP_RV370_5460 0x5460
#define PCI_CHIP_RV370_5464 0x5464
#define PCI_CHIP_RS300_5834 0x5834
#define PCI_CHIP_RS300_5835 0x5835
#define PCI_CHIP_RS300_5836 0x5836
#define PCI_CHIP_RS300_5837 0x5837
#define PCI_CHIP_RV280_5960 0x5960
#define PCI_CHIP_RV280_5961 0x5961
#define PCI_CHIP_RV280_5962 0x5962
#define PCI_CHIP_RV280_5964 0x5964
#define PCI_CHIP_RV280_5965 0x5965
#define PCI_CHIP_RN50_5969 0x5969
#define PCI_CHIP_RV370_5B60 0x5B60
#define PCI_CHIP_RV370_5B62 0x5B62
#define PCI_CHIP_RV370_5B64 0x5B64
#define PCI_CHIP_RV370_5B65 0x5B65
#define PCI_CHIP_RV280_5C61 0x5C61
#define PCI_CHIP_RV280_5C63 0x5C63
enum {
CHIP_FAMILY_R100,
CHIP_FAMILY_RV100,
CHIP_FAMILY_RS100,
CHIP_FAMILY_RV200,
CHIP_FAMILY_RS200,
CHIP_FAMILY_R200,
CHIP_FAMILY_RV250,
CHIP_FAMILY_RS300,
CHIP_FAMILY_RV280,
CHIP_FAMILY_R300,
CHIP_FAMILY_R350,
CHIP_FAMILY_RV350,
CHIP_FAMILY_RV380,
CHIP_FAMILY_R420,
CHIP_FAMILY_LAST
};
/* General classes of Radeons, as described above the device ID section */
#define RADEON_CLASS_R100 (0 << 0)
#define RADEON_CLASS_R200 (1 << 0)
#define RADEON_CLASS_R300 (2 << 0)
#define RADEON_CLASS_MASK (3 << 0)
#define RADEON_CHIPSET_TCL (1 << 2) /* tcl support - any radeon */
#define RADEON_CHIPSET_BROKEN_STENCIL (1 << 3) /* r100 stencil bug */
#define R200_CHIPSET_YCBCR_BROKEN (1 << 4) /* r200 ycbcr bug */
#endif /* _RADEON_CHIPSET_H */

8
src/mesa/drivers/dri/radeon/radeon_context.c
View file

@ -464,15 +464,15 @@ radeonCreateContext( const __GLcontextModes *glVisual,
fprintf(stderr, "disabling 3D acceleration\n");
FALLBACK(rmesa, RADEON_FALLBACK_DISABLE, 1);
} else if (tcl_mode == DRI_CONF_TCL_SW ||
!(rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL)) {
if (rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL) {
rmesa->radeonScreen->chipset &= ~RADEON_CHIPSET_TCL;
!(rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
if (rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
rmesa->radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL;
fprintf(stderr, "Disabling HW TCL support\n");
}
TCL_FALLBACK(rmesa->glCtx, RADEON_TCL_FALLBACK_TCL_DISABLE, 1);
}
if (rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL) {
if (rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
if (tcl_mode >= DRI_CONF_TCL_VTXFMT)
radeonVtxfmtInit( ctx, tcl_mode >= DRI_CONF_TCL_CODEGEN );

2
src/mesa/drivers/dri/radeon/radeon_ioctl.c
View file

@ -210,7 +210,7 @@ void radeonEmitState( radeonContextPtr rmesa )
foreach(atom, &rmesa->hw.atomlist) {
if (rmesa->hw.all_dirty)
atom->dirty = GL_TRUE;
if (!(rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL) &&
if (!(rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL) &&
atom->is_tcl)
atom->dirty = GL_FALSE;
if (atom->dirty) {

444
src/mesa/drivers/dri/radeon/radeon_screen.c
View file

@ -43,10 +43,20 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "renderbuffer.h"
#define STANDALONE_MMIO
#include "radeon_context.h"
#include "radeon_screen.h"
#include "radeon_chipset.h"
#include "radeon_macros.h"
#include "radeon_screen.h"
#if !RADEON_COMMON
#include "radeon_context.h"
#include "radeon_span.h"
#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
#include "r200_context.h"
#include "r200_ioctl.h"
#include "r200_span.h"
#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
#include "r300_context.h"
#include "radeon_span.h"
#endif
#include "utils.h"
#include "context.h"
@ -59,6 +69,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include "xmlpool.h"
#if !RADEON_COMMON /* R100 */
PUBLIC const char __driConfigOptions[] =
DRI_CONF_BEGIN
DRI_CONF_SECTION_PERFORMANCE
@ -84,41 +95,118 @@ DRI_CONF_BEGIN
DRI_CONF_END;
static const GLuint __driNConfigOptions = 14;
#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
PUBLIC const char __driConfigOptions[] =
DRI_CONF_BEGIN
DRI_CONF_SECTION_PERFORMANCE
DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
DRI_CONF_MAX_TEXTURE_UNITS(4,2,6)
DRI_CONF_HYPERZ(false)
DRI_CONF_SECTION_END
DRI_CONF_SECTION_QUALITY
DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
DRI_CONF_NO_NEG_LOD_BIAS(false)
DRI_CONF_FORCE_S3TC_ENABLE(false)
DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
DRI_CONF_TEXTURE_LEVEL_HACK(false)
DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
DRI_CONF_SECTION_END
DRI_CONF_SECTION_DEBUG
DRI_CONF_NO_RAST(false)
DRI_CONF_SECTION_END
DRI_CONF_SECTION_SOFTWARE
DRI_CONF_ARB_VERTEX_PROGRAM(false)
DRI_CONF_NV_VERTEX_PROGRAM(false)
DRI_CONF_SECTION_END
DRI_CONF_END;
static const GLuint __driNConfigOptions = 17;
extern const struct dri_extension blend_extensions[];
extern const struct dri_extension ARB_vp_extension[];
extern const struct dri_extension NV_vp_extension[];
extern const struct dri_extension ATI_fs_extension[];
#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
/* TODO: integrate these into xmlpool.h! */
#define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
DRI_CONF_DESC(en,"Number of texture image units") \
DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
DRI_CONF_OPT_END
#define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
DRI_CONF_DESC(en,"Number of texture coordinate units") \
DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
DRI_CONF_OPT_END
#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
DRI_CONF_OPT_END
const char __driConfigOptions[] =
DRI_CONF_BEGIN
DRI_CONF_SECTION_PERFORMANCE
DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(16, 2, 16)
DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
DRI_CONF_SECTION_END
DRI_CONF_SECTION_QUALITY
DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
DRI_CONF_NO_NEG_LOD_BIAS(false)
DRI_CONF_FORCE_S3TC_ENABLE(false)
DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
DRI_CONF_SECTION_END
DRI_CONF_SECTION_DEBUG
DRI_CONF_NO_RAST(false)
DRI_CONF_SECTION_END
DRI_CONF_END;
static const GLuint __driNConfigOptions = 14;
#ifndef RADEON_DEBUG
int RADEON_DEBUG = 0;
static const struct dri_debug_control debug_control[] = {
{"fall", DEBUG_FALLBACKS},
{"tex", DEBUG_TEXTURE},
{"ioctl", DEBUG_IOCTL},
{"prim", DEBUG_PRIMS},
{"vert", DEBUG_VERTS},
{"state", DEBUG_STATE},
{"code", DEBUG_CODEGEN},
{"vfmt", DEBUG_VFMT},
{"vtxf", DEBUG_VFMT},
{"verb", DEBUG_VERBOSE},
{"dri", DEBUG_DRI},
{"dma", DEBUG_DMA},
{"san", DEBUG_SANITY},
{"sync", DEBUG_SYNC},
{"pix", DEBUG_PIXEL},
{"mem", DEBUG_MEMORY},
{"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */
{NULL, 0}
};
#endif /* RADEON_DEBUG */
#endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */
extern const struct dri_extension card_extensions[];
#if 1
/* Including xf86PciInfo.h introduces a bunch of errors...
*/
#define PCI_CHIP_RADEON_QD 0x5144
#define PCI_CHIP_RADEON_QE 0x5145
#define PCI_CHIP_RADEON_QF 0x5146
#define PCI_CHIP_RADEON_QG 0x5147
#define PCI_CHIP_RADEON_QY 0x5159
#define PCI_CHIP_RADEON_QZ 0x515A
#define PCI_CHIP_RN50_515E 0x515E
#define PCI_CHIP_RN50_5969 0x5969
#define PCI_CHIP_RADEON_LW 0x4C57 /* mobility 7 - has tcl */
#define PCI_CHIP_RADEON_LX 0x4C58 /* mobility FireGL 7800 m7 */
#define PCI_CHIP_RADEON_LY 0x4C59
#define PCI_CHIP_RADEON_LZ 0x4C5A
#define PCI_CHIP_RV200_QW 0x5157 /* Radeon 7500 - not an R200 at all */
#define PCI_CHIP_RV200_QX 0x5158
/* IGP Chipsets */
#define PCI_CHIP_RS100_4136 0x4136
#define PCI_CHIP_RS200_4137 0x4137
#define PCI_CHIP_RS250_4237 0x4237
#define PCI_CHIP_RS100_4336 0x4336
#define PCI_CHIP_RS200_4337 0x4337
#define PCI_CHIP_RS250_4437 0x4437
#endif
static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo );
static __GLcontextModes *
@ -227,6 +315,10 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
return NULL;
}
#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control);
#endif
/* parse information in __driConfigOptions */
driParseOptionInfo (&screen->optionCache,
__driConfigOptions, __driNConfigOptions);
@ -252,6 +344,17 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
}
if (sPriv->drmMinor >= 6) {
gp.param = RADEON_PARAM_GART_BASE;
gp.value = &screen->gart_base;
ret = drmCommandWriteRead( sPriv->fd, DRM_RADEON_GETPARAM,
&gp, sizeof(gp));
if (ret) {
FREE( screen );
fprintf(stderr, "drmR200GetParam (RADEON_PARAM_GART_BASE): %d\n", ret);
return NULL;
}
gp.param = RADEON_PARAM_IRQ_NR;
gp.value = &screen->irq;
@ -262,7 +365,11 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret);
return NULL;
}
screen->drmSupportsCubeMaps = (sPriv->drmMinor >= 15);
screen->drmSupportsCubeMaps = (sPriv->drmMinor >= 7);
screen->drmSupportsBlendColor = (sPriv->drmMinor >= 11);
screen->drmSupportsTriPerf = (sPriv->drmMinor >= 16);
screen->drmSupportsFragShader = (sPriv->drmMinor >= 18);
screen->drmSupportsPointSprites = (sPriv->drmMinor >= 13);
}
}
@ -322,36 +429,168 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
: ( ( INREG( RADEON_MC_AGP_LOCATION ) & 0x0ffffU ) << 16 ) );
}
screen->chipset = 0;
screen->chip_flags = 0;
/* XXX: add more chipsets */
switch ( dri_priv->deviceID ) {
default:
fprintf(stderr, "unknown chip id, assuming full radeon support\n");
case PCI_CHIP_RADEON_LY:
case PCI_CHIP_RADEON_LZ:
case PCI_CHIP_RADEON_QY:
case PCI_CHIP_RADEON_QZ:
case PCI_CHIP_RN50_515E:
case PCI_CHIP_RN50_5969:
screen->chip_family = CHIP_FAMILY_RV100;
break;
case PCI_CHIP_RS100_4136:
case PCI_CHIP_RS100_4336:
screen->chip_family = CHIP_FAMILY_RS100;
break;
case PCI_CHIP_RS200_4137:
case PCI_CHIP_RS200_4337:
case PCI_CHIP_RS250_4237:
case PCI_CHIP_RS250_4437:
screen->chip_family = CHIP_FAMILY_RS200;
break;
case PCI_CHIP_RADEON_QD:
case PCI_CHIP_RADEON_QE:
case PCI_CHIP_RADEON_QF:
case PCI_CHIP_RADEON_QG:
/* all original radeons (7200) presumably have a stencil op bug */
screen->chipset |= RADEON_CHIPSET_BROKEN_STENCIL;
screen->chip_family = CHIP_FAMILY_R100;
screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL;
break;
case PCI_CHIP_RV200_QW:
case PCI_CHIP_RV200_QX:
case PCI_CHIP_RADEON_LW:
case PCI_CHIP_RADEON_LX:
screen->chipset |= RADEON_CHIPSET_TCL;
case PCI_CHIP_RADEON_QY:
case PCI_CHIP_RADEON_QZ:
case PCI_CHIP_RN50_515E:
case PCI_CHIP_RN50_5969:
case PCI_CHIP_RADEON_LY:
case PCI_CHIP_RADEON_LZ:
case PCI_CHIP_RS100_4136: /* IGPs don't have TCL */
case PCI_CHIP_RS200_4137:
case PCI_CHIP_RS250_4237:
case PCI_CHIP_RS100_4336:
case PCI_CHIP_RS200_4337:
case PCI_CHIP_RS250_4437:
screen->chip_family = CHIP_FAMILY_RV200;
screen->chip_flags = RADEON_CHIPSET_TCL;
break;
case PCI_CHIP_R200_BB:
case PCI_CHIP_R200_BC:
case PCI_CHIP_R200_QH:
case PCI_CHIP_R200_QI:
case PCI_CHIP_R200_QJ:
case PCI_CHIP_R200_QK:
case PCI_CHIP_R200_QL:
case PCI_CHIP_R200_QM:
case PCI_CHIP_R200_QN:
case PCI_CHIP_R200_QO:
screen->chip_family = CHIP_FAMILY_R200;
screen->chip_flags = RADEON_CHIPSET_TCL;
break;
case PCI_CHIP_RV250_Id:
case PCI_CHIP_RV250_Ie:
case PCI_CHIP_RV250_If:
case PCI_CHIP_RV250_Ig:
case PCI_CHIP_RV250_Ld:
case PCI_CHIP_RV250_Le:
case PCI_CHIP_RV250_Lf:
case PCI_CHIP_RV250_Lg:
screen->chip_family = CHIP_FAMILY_RV250;
screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL;
break;
case PCI_CHIP_RV280_5960:
case PCI_CHIP_RV280_5961:
case PCI_CHIP_RV280_5962:
case PCI_CHIP_RV280_5964:
case PCI_CHIP_RV280_5965:
case PCI_CHIP_RV280_5C61:
case PCI_CHIP_RV280_5C63:
screen->chip_family = CHIP_FAMILY_RV280;
screen->chip_flags = RADEON_CHIPSET_TCL;
break;
case PCI_CHIP_RS300_5834:
case PCI_CHIP_RS300_5835:
case PCI_CHIP_RS300_5836:
case PCI_CHIP_RS300_5837:
screen->chip_family = CHIP_FAMILY_RS300;
break;
case PCI_CHIP_R300_AD:
case PCI_CHIP_R300_AE:
case PCI_CHIP_R300_AF:
case PCI_CHIP_R300_AG:
case PCI_CHIP_R300_ND:
case PCI_CHIP_R300_NE:
case PCI_CHIP_R300_NF:
case PCI_CHIP_R300_NG:
screen->chip_family = CHIP_FAMILY_R300;
screen->chip_flags = RADEON_CHIPSET_TCL;
break;
case PCI_CHIP_RV350_AP:
case PCI_CHIP_RV350_AQ:
case PCI_CHIP_RV350_AR:
case PCI_CHIP_RV350_AS:
case PCI_CHIP_RV350_AT:
case PCI_CHIP_RV350_AV:
case PCI_CHIP_RV350_AU:
case PCI_CHIP_RV350_NP:
case PCI_CHIP_RV350_NQ:
case PCI_CHIP_RV350_NR:
case PCI_CHIP_RV350_NS:
case PCI_CHIP_RV350_NT:
case PCI_CHIP_RV350_NV:
screen->chip_family = CHIP_FAMILY_RV350;
screen->chip_flags = RADEON_CHIPSET_TCL;
break;
case PCI_CHIP_R350_AH:
case PCI_CHIP_R350_AI:
case PCI_CHIP_R350_AJ:
case PCI_CHIP_R350_AK:
case PCI_CHIP_R350_NH:
case PCI_CHIP_R350_NI:
case PCI_CHIP_R360_NJ:
case PCI_CHIP_R350_NK:
screen->chip_family = CHIP_FAMILY_R350;
screen->chip_flags = RADEON_CHIPSET_TCL;
break;
case PCI_CHIP_RV370_5460:
case PCI_CHIP_RV370_5464:
case PCI_CHIP_RV370_5B60:
case PCI_CHIP_RV370_5B62:
case PCI_CHIP_RV370_5B64:
case PCI_CHIP_RV370_5B65:
screen->chip_family = CHIP_FAMILY_RV380;
screen->chip_flags = RADEON_CHIPSET_TCL;
break;
case PCI_CHIP_R420_JN:
case PCI_CHIP_R420_JH:
case PCI_CHIP_R420_JI:
case PCI_CHIP_R420_JJ:
case PCI_CHIP_R420_JK:
case PCI_CHIP_R420_JL:
case PCI_CHIP_R420_JM:
case PCI_CHIP_R420_JO:
case PCI_CHIP_R420_JP:
screen->chip_family = CHIP_FAMILY_R420;
screen->chip_flags = RADEON_CHIPSET_TCL;
break;
default:
fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
dri_priv->deviceID);
return NULL;
}
if (screen->chip_family <= CHIP_FAMILY_RS200)
screen->chip_flags |= RADEON_CLASS_R200;
else if (screen->chip_family <= CHIP_FAMILY_RV280)
screen->chip_flags |= RADEON_CLASS_R200;
else
screen->chip_flags |= RADEON_CLASS_R300;
screen->cpp = dri_priv->bpp / 8;
screen->AGPMode = dri_priv->AGPMode;
@ -376,7 +615,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
/* Check if ddx has set up a surface reg to cover depth buffer */
screen->depthHasSurface = ((sPriv->ddxMajor > 4) &&
(screen->chipset & RADEON_CHIPSET_TCL));
(screen->chip_flags & RADEON_CHIPSET_TCL));
screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
+ screen->fbLocation;
@ -406,8 +645,18 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
}
(*glx_enable_extension)( psc, "GLX_MESA_swap_frame_usage" );
if (IS_R200_CLASS(screen))
(*glx_enable_extension)( psc, "GLX_MESA_allocate_memory" );
}
#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
if (IS_R200_CLASS(screen)) {
sPriv->psc->allocateMemory = (void *) r200AllocateMemoryMESA;
sPriv->psc->freeMemory = (void *) r200FreeMemoryMESA;
sPriv->psc->memoryOffset = (void *) r200GetMemoryOffsetMESA;
}
#endif
screen->driScreen = sPriv;
screen->sarea_priv_offset = dri_priv->sarea_priv_offset;
return screen;
@ -559,6 +808,38 @@ radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv)
_mesa_destroy_framebuffer((GLframebuffer *) (driDrawPriv->driverPrivate));
}
#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
/**
* Choose the appropriate CreateContext function based on the chipset.
* Eventually, all drivers will go through this process.
*/
static GLboolean radeonCreateContext(const __GLcontextModes * glVisual,
__DRIcontextPrivate * driContextPriv,
void *sharedContextPriv)
{
__DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
if (IS_R300_CLASS(screen))
return r300CreateContext(glVisual, driContextPriv, sharedContextPriv);
return GL_FALSE;
}
/**
* Choose the appropriate DestroyContext function based on the chipset.
*/
static void radeonDestroyContext(__DRIcontextPrivate * driContextPriv)
{
radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate;
if (IS_R300_CLASS(radeon->radeonScreen))
return r300DestroyContext(driContextPriv);
}
#endif
#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
static struct __DriverAPIRec radeonAPI = {
.InitDriver = radeonInitDriver,
.DestroyScreen = radeonDestroyScreen,
@ -575,7 +856,24 @@ static struct __DriverAPIRec radeonAPI = {
.WaitForSBC = NULL,
.SwapBuffersMSC = NULL
};
#else
static const struct __DriverAPIRec r200API = {
.InitDriver = radeonInitDriver,
.DestroyScreen = radeonDestroyScreen,
.CreateContext = r200CreateContext,
.DestroyContext = r200DestroyContext,
.CreateBuffer = radeonCreateBuffer,
.DestroyBuffer = radeonDestroyBuffer,
.SwapBuffers = r200SwapBuffers,
.MakeCurrent = r200MakeCurrent,
.UnbindContext = r200UnbindContext,
.GetSwapInfo = getSwapInfo,
.GetMSC = driGetMSC32,
.WaitForMSC = driWaitForMSC32,
.WaitForSBC = NULL,
.SwapBuffersMSC = NULL
};
#endif
/**
* This is the bootstrap function for the driver. libGL supplies all of the
@ -601,23 +899,43 @@ __driCreateNewScreen_20050727( __DRInativeDisplay *dpy,
__GLcontextModes ** driver_modes )
{
__DRIscreenPrivate *psp;
#if !RADEON_COMMON
static const char *driver_name = "Radeon";
static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
static const __DRIversion dri_expected = { 4, 0, 0 };
static const __DRIversion drm_expected = { 1, 3, 0 };
#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
static const char *driver_name = "R200";
static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
static const __DRIversion dri_expected = { 4, 0, 0 };
static const __DRIversion drm_expected = { 1, 5, 0 };
#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
static const char *driver_name = "R300";
static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
static const __DRIversion dri_expected = { 4, 0, 0 };
static const __DRIversion drm_expected = { 1, 17, 0 };
#endif
dri_interface = interface;
if ( ! driCheckDriDdxDrmVersions3( "Radeon",
if ( ! driCheckDriDdxDrmVersions3( driver_name,
dri_version, & dri_expected,
ddx_version, & ddx_expected,
drm_version, & drm_expected ) ) {
return NULL;
}
#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
psp = __driUtilCreateNewScreen(dpy, scrn, psc, NULL,
ddx_version, dri_version, drm_version,
frame_buffer, pSAREA, fd,
internal_api_version, &radeonAPI);
#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
psp = __driUtilCreateNewScreen(dpy, scrn, psc, NULL,
ddx_version, dri_version, drm_version,
frame_buffer, pSAREA, fd,
internal_api_version, &r200API);
#endif
if ( psp != NULL ) {
RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv;
*driver_modes = radeonFillInModes( dri_priv->bpp,
@ -636,6 +954,12 @@ __driCreateNewScreen_20050727( __DRInativeDisplay *dpy,
* Hello chicken. Hello egg. How are you two today?
*/
driInitExtensions( NULL, card_extensions, GL_FALSE );
#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
driInitExtensions( NULL, blend_extensions, GL_FALSE );
driInitSingleExtension( NULL, ARB_vp_extension );
driInitSingleExtension( NULL, NV_vp_extension );
driInitSingleExtension( NULL, ATI_fs_extension );
#endif
}
return (void *) psp;
@ -648,7 +972,11 @@ __driCreateNewScreen_20050727( __DRInativeDisplay *dpy,
static int
getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo )
{
#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
radeonContextPtr rmesa;
#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
r200ContextPtr rmesa;
#endif
if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL)
|| (dPriv->driContextPriv->driverPrivate == NULL)
@ -656,7 +984,7 @@ getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo )
return -1;
}
rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate;
rmesa = dPriv->driContextPriv->driverPrivate;
sInfo->swap_count = rmesa->swap_count;
sInfo->swap_ust = rmesa->swap_ust;
sInfo->swap_missed_count = rmesa->swap_missed_count;

25
src/mesa/drivers/dri/radeon/radeon_screen.h
View file

@ -41,8 +41,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
* IMPORTS: these headers contain all the DRI, X and kernel-related
* definitions that we need.
*/
/* #include "dri_util.h" */
#include "dri_util.h"
#include "radeon_dri.h"
#include "radeon_chipset.h"
#include "radeon_reg.h"
#include "drm_sarea.h"
#include "xmlconfig.h"
@ -54,13 +55,9 @@ typedef struct {
drmAddress map; /* Mapping of the DRM region */
} radeonRegionRec, *radeonRegionPtr;
/* chipset features */
#define RADEON_CHIPSET_TCL (1 << 0)
#define RADEON_CHIPSET_BROKEN_STENCIL (1 << 1)
typedef struct {
int chipset;
int chip_family;
int chip_flags;
int cpp;
int IsPCI; /* Current card is a PCI card */
int AGPMode;
@ -93,12 +90,24 @@ typedef struct {
unsigned int sarea_priv_offset;
unsigned int gart_buffer_offset; /* offset in card memory space */
unsigned int gart_texture_offset; /* offset in card memory space */
unsigned int gart_base;
GLboolean drmSupportsCubeMaps; /* need radeon kernel module >= 1.7 */
GLboolean drmSupportsBlendColor; /* need radeon kernel module >= 1.11 */
GLboolean drmSupportsTriPerf; /* need radeon kernel module >= 1.16 */
GLboolean drmSupportsFragShader; /* need radeon kernel module >= 1.18 */
GLboolean drmSupportsPointSprites; /* need radeon kernel module >= 1.13 */
GLboolean depthHasSurface;
/* Configuration cache with default values for all contexts */
driOptionCache optionCache;
GLboolean drmSupportsCubeMaps;
} radeonScreenRec, *radeonScreenPtr;
#define IS_R100_CLASS(screen) \
((screen->chip_flags & RADEON_CLASS_MASK) == RADEON_CLASS_R100)
#define IS_R200_CLASS(screen) \
((screen->chip_flags & RADEON_CLASS_MASK) == RADEON_CLASS_R200)
#define IS_R300_CLASS(screen) \
((screen->chip_flags & RADEON_CLASS_MASK) == RADEON_CLASS_R300)
#endif /* __RADEON_SCREEN_H__ */

2
src/mesa/drivers/dri/radeon/radeon_state.c
View file

@ -1348,7 +1348,7 @@ static void radeonStencilOpSeparate( GLcontext *ctx, GLenum face, GLenum fail,
GLuint tempRADEON_STENCIL_ZPASS_DEC_WRAP;
GLuint tempRADEON_STENCIL_ZPASS_INC_WRAP;
if (rmesa->radeonScreen->chipset & RADEON_CHIPSET_BROKEN_STENCIL) {
if (rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_BROKEN_STENCIL) {
tempRADEON_STENCIL_FAIL_DEC_WRAP = RADEON_STENCIL_FAIL_DEC;
tempRADEON_STENCIL_FAIL_INC_WRAP = RADEON_STENCIL_FAIL_INC;
tempRADEON_STENCIL_ZFAIL_DEC_WRAP = RADEON_STENCIL_ZFAIL_DEC;

4
src/mesa/drivers/dri/radeon/radeon_state_init.c
View file

@ -376,7 +376,7 @@ void radeonInitState( radeonContextPtr rmesa )
if (rmesa->using_hyperz) {
rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_COMPRESSION_ENABLE |
RADEON_Z_DECOMPRESSION_ENABLE;
if (rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL) {
if (rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
/* works for q3, but slight rendering errors with glxgears ? */
/* rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
/* need this otherwise get lots of lockups with q3 ??? */
@ -446,7 +446,7 @@ void radeonInitState( radeonContextPtr rmesa )
RADEON_VC_NO_SWAP;
#endif
if (!(rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL)) {
if (!(rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] |= RADEON_TCL_BYPASS;
}