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panvk,panfrost: Pass inputs and info to postprocess

Browse source 
This is needed if we want postprocess to decide IDVS and layout later in
the series

Signed-off-by: Lorenzo Rossi <lorenzo.rossi@collabora.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40924>
This commit is contained in:
Lorenzo Rossi 2026-04-13 10:41:05 +02:00 • committed by Marge Bot
parent 01e6a0555c
commit 39f54ddea2
12 changed files with 35 additions and 26 deletions
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2
src/gallium/drivers/panfrost/pan_blend_cso.c
View file

@ -114,7 +114,7 @@ GENX(pan_blend_get_shader_locked)(struct pan_blend_shader_cache *cache,
pan_prod_id(cache->gpu_id) < 0x700);
#endif
pan_postprocess_nir(nir, inputs.gpu_id);
pan_postprocess_nir(nir, &inputs, &info);
struct util_dynarray binary;
binary = UTIL_DYNARRAY_INIT;

2
src/gallium/drivers/panfrost/pan_fb_preload.c
View file

@ -541,7 +541,7 @@ pan_preload_get_shader(struct pan_fb_preload_cache *cache,
BITSET_SET(b.shader->info.textures_used, i);
pan_preprocess_nir(b.shader, inputs.gpu_id);
pan_postprocess_nir(b.shader, inputs.gpu_id);
pan_postprocess_nir(b.shader, &inputs, &shader->info);
if (PAN_ARCH == 4) {
NIR_PASS(_, b.shader, nir_shader_intrinsics_pass,

2
src/gallium/drivers/panfrost/pan_shader.c
View file

@ -186,7 +186,7 @@ panfrost_shader_compile(struct panfrost_screen *screen, const nir_shader *ir,
/* Lower resource indices */
NIR_PASS(_, s, panfrost_nir_lower_res_indices, &inputs);
pan_postprocess_nir(s, panfrost_device_gpu_id(dev));
pan_postprocess_nir(s, &inputs, &out->info);
if (s->info.stage == MESA_SHADER_VERTEX) {
NIR_PASS(_, s, nir_inline_sysval,

12
src/panfrost/clc/pan_compile.c
View file

@ -428,7 +428,12 @@ main(int argc, const char **argv)
nir_var_mem_shared | nir_var_mem_global,
nir_address_format_62bit_generic);
pan_postprocess_nir(s, inputs.gpu_id);
struct pan_shader_info shader_info = {0};
if (target_arch >= 9)
shader_info.cs.allow_merging_workgroups =
valhall_can_merge_workgroups(s);
pan_postprocess_nir(s, &inputs, &shader_info);
NIR_PASS(_, s, nir_shader_intrinsics_pass, lower_sysvals,
nir_metadata_control_flow, NULL);
@ -436,13 +441,8 @@ main(int argc, const char **argv)
nir_shader *clone = nir_shader_clone(NULL, s);
struct util_dynarray shader_binary;
struct pan_shader_info shader_info = {0};
shader_binary = UTIL_DYNARRAY_INIT;
if (target_arch >= 9)
shader_info.cs.allow_merging_workgroups =
valhall_can_merge_workgroups(s);
pan_shader_compile(clone, &inputs, &shader_binary, &shader_info);
assert(shader_info.push.count * 4 <=

4
src/panfrost/compiler/bifrost/bifrost_compile.h
View file

@ -64,7 +64,9 @@ bifrost_precompiled_kernel_prepare_push_uniforms(
void bifrost_preprocess_nir(nir_shader *nir, uint64_t gpu_id);
void bifrost_optimize_nir(nir_shader *nir, uint64_t gpu_id);
void bifrost_postprocess_nir(nir_shader *nir, uint64_t gpu_id);
void bifrost_postprocess_nir(nir_shader *nir,
const struct pan_compile_inputs *inputs,
struct pan_shader_info *info);
void bifrost_compile_shader_nir(nir_shader *nir,
const struct pan_compile_inputs *inputs,

15
src/panfrost/compiler/bifrost/bifrost_nir.c
View file

@ -847,10 +847,15 @@ nir_shader_has_local_variables(const nir_shader *nir)
}
void
bifrost_postprocess_nir(nir_shader *nir, uint64_t gpu_id)
bifrost_postprocess_nir(nir_shader *nir,
const struct pan_compile_inputs *inputs,
struct pan_shader_info *info)
{
MESA_TRACE_FUNC();
const uint64_t gpu_id = inputs->gpu_id;
const unsigned gpu_arch = pan_arch(gpu_id);
/* We assume that UBO and SSBO were lowered, let's move things around. */
nir_move_options move_all = nir_move_const_undef | nir_move_load_ubo |
nir_move_comparisons | nir_move_copies |
@ -924,8 +929,8 @@ bifrost_postprocess_nir(nir_shader *nir, uint64_t gpu_id)
NIR_PASS(_, nir, nir_lower_mem_access_bit_sizes, &mem_size_options);
nir_lower_ssbo_options ssbo_opts = {
.native_loads = pan_arch(gpu_id) >= 9,
.native_offset = pan_arch(gpu_id) >= 9,
.native_loads = gpu_arch >= 9,
.native_offset = gpu_arch >= 9,
};
NIR_PASS(_, nir, nir_lower_ssbo, &ssbo_opts);
@ -969,11 +974,11 @@ bifrost_postprocess_nir(nir_shader *nir, uint64_t gpu_id)
NIR_PASS(_, nir, nir_lower_vars_to_ssa);
NIR_PASS(_, nir, nir_shader_intrinsics_pass, bi_lower_subgroups,
nir_metadata_control_flow, &gpu_id);
nir_metadata_control_flow, (void *) &gpu_id);
NIR_PASS(_, nir, nir_lower_64bit_phis);
NIR_PASS(_, nir, nir_lower_int64);
NIR_PASS(_, nir, nir_lower_bit_size, bi_lower_bit_size, &gpu_id);
NIR_PASS(_, nir, nir_lower_bit_size, bi_lower_bit_size, (void *) &gpu_id);
NIR_PASS(_, nir, nir_opt_idiv_const, 8);
NIR_PASS(_, nir, nir_lower_idiv,

13
src/panfrost/compiler/pan_compiler.c
View file

@ -91,12 +91,15 @@ pan_optimize_nir(nir_shader *nir, uint64_t gpu_id)
}
void
pan_postprocess_nir(nir_shader *nir, uint64_t gpu_id)
pan_postprocess_nir(nir_shader *nir, const struct pan_compile_inputs *inputs,
struct pan_shader_info *info)
{
if (pan_arch(gpu_id) >= 6)
bifrost_postprocess_nir(nir, gpu_id);
memset(info, 0, sizeof(*info));
if (pan_arch(inputs->gpu_id) >= 6)
bifrost_postprocess_nir(nir, inputs, info);
else
midgard_postprocess_nir(nir, gpu_id);
midgard_postprocess_nir(nir, inputs->gpu_id);
}
/** Converts a per-component mask to a byte mask */
@ -273,8 +276,6 @@ pan_shader_compile(nir_shader *s, struct pan_compile_inputs *inputs,
{
unsigned arch = pan_arch(inputs->gpu_id);
memset(info, 0, sizeof(*info));
NIR_PASS(_, s, nir_inline_sysval, nir_intrinsic_load_printf_buffer_size,
PAN_PRINTF_BUFFER_SIZE - 8);

4
src/panfrost/compiler/pan_compiler.h
View file

@ -71,7 +71,9 @@ struct pan_compile_inputs {
*/
void pan_preprocess_nir(nir_shader *nir, uint64_t gpu_id);
void pan_optimize_nir(nir_shader *nir, uint64_t gpu_id);
void pan_postprocess_nir(nir_shader *nir, uint64_t gpu_id);
void pan_postprocess_nir(nir_shader *nir,
const struct pan_compile_inputs *inputs,
struct pan_shader_info *info);
void pan_shader_compile(nir_shader *nir, struct pan_compile_inputs *inputs,
struct util_dynarray *binary,

1
src/panfrost/vulkan/bifrost/panvk_vX_meta_desc_copy.c
View file

@ -351,7 +351,6 @@ panvk_meta_desc_copy_rsd(struct panvk_device *dev)
};
pan_preprocess_nir(b.shader, inputs.gpu_id);
pan_postprocess_nir(b.shader, inputs.gpu_id);
VkResult result = panvk_per_arch(create_internal_shader)(
dev, b.shader, &inputs, &shader);

1
src/panfrost/vulkan/panvk_vX_blend.c
View file

@ -93,7 +93,6 @@ get_blend_shader(struct panvk_device *dev,
};
pan_preprocess_nir(nir, inputs.gpu_id);
pan_postprocess_nir(nir, inputs.gpu_id);
VkResult result =
panvk_per_arch(create_internal_shader)(dev, nir, &inputs, &shader);

1
src/panfrost/vulkan/panvk_vX_cmd_frame_shaders.c
View file

@ -221,7 +221,6 @@ get_frame_shader(struct panvk_device *dev,
};
pan_preprocess_nir(nir, inputs.gpu_id);
pan_postprocess_nir(nir, inputs.gpu_id);
VkResult result = panvk_per_arch(create_internal_shader)(
dev, nir, &inputs, &shader);

4
src/panfrost/vulkan/panvk_vX_shader.c
View file

@ -979,7 +979,7 @@ panvk_compile_nir(struct panvk_device *dev, nir_shader *nir,
NIR_PASS(_, nir, pan_nir_lower_texel_buffer_fetch_index, MAX_VS_ATTRIBS);
}
pan_postprocess_nir(nir, input.gpu_id);
pan_postprocess_nir(nir, &input, &shader->info);
if (noperspective_varyings && nir->info.stage == MESA_SHADER_VERTEX) {
NIR_PASS(_, nir, nir_inline_sysval,
@ -2472,6 +2472,8 @@ panvk_per_arch(create_internal_shader)(
panvk_per_arch(compiler_lock)();
pan_postprocess_nir(nir, compiler_inputs, &shader->info);
util_dynarray_init(&binary, nir);
pan_shader_compile(nir, compiler_inputs, &binary, &shader->info);