From 39cd8d6d24186bdc2a1ebdf2861283d3f3528519 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Tue, 18 Nov 2025 13:35:30 -0800 Subject: [PATCH] freedreno: Move SP_DBG_ECO_CNTL to raw_magic_regs Signed-off-by: Rob Clark Part-of: --- src/freedreno/common/freedreno_dev_info.h | 1 - src/freedreno/common/freedreno_devices.py | 36 +++++++++---------- src/freedreno/vulkan/tu_cmd_buffer.cc | 2 -- .../drivers/freedreno/a6xx/fd6_emit.cc | 1 - 4 files changed, 18 insertions(+), 22 deletions(-) diff --git a/src/freedreno/common/freedreno_dev_info.h b/src/freedreno/common/freedreno_dev_info.h index de2b49081d5..b4f253f4c79 100644 --- a/src/freedreno/common/freedreno_dev_info.h +++ b/src/freedreno/common/freedreno_dev_info.h @@ -227,7 +227,6 @@ struct fd_dev_info { bool is_a702; struct { - uint32_t SP_DBG_ECO_CNTL; uint32_t RB_DBG_ECO_CNTL; uint32_t RB_DBG_ECO_CNTL_blit; uint32_t HLSQ_DBG_ECO_CNTL; diff --git a/src/freedreno/common/freedreno_devices.py b/src/freedreno/common/freedreno_devices.py index 7ca81e30aac..5bfc61ad023 100644 --- a/src/freedreno/common/freedreno_devices.py +++ b/src/freedreno/common/freedreno_devices.py @@ -468,7 +468,6 @@ add_gpus([ ubwc_swizzle = 0x7, macrotile_mode = 0, magic_regs = dict( - SP_DBG_ECO_CNTL = 0x0, RB_DBG_ECO_CNTL = 0x04100000, RB_DBG_ECO_CNTL_blit = 0x04100000, HLSQ_DBG_ECO_CNTL = 0, @@ -483,6 +482,7 @@ add_gpus([ [A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL, 0], [A6XXRegs.REG_A6XX_GRAS_DBG_ECO_CNTL, 0], [A6XXRegs.REG_A6XX_SP_CHICKEN_BITS, 0], + [A6XXRegs.REG_A6XX_SP_DBG_ECO_CNTL, 0], [A6XXRegs.REG_A6XX_UCHE_CLIENT_PF, 0x00000004], ], )) @@ -505,7 +505,6 @@ add_gpus([ highest_bank_bit = 14, macrotile_mode = 0, magic_regs = dict( - SP_DBG_ECO_CNTL = 0x0, RB_DBG_ECO_CNTL = 0x04100000, RB_DBG_ECO_CNTL_blit = 0x04100000, HLSQ_DBG_ECO_CNTL = 0x00080000, @@ -520,6 +519,7 @@ add_gpus([ [A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL, 0x00108000], [A6XXRegs.REG_A6XX_GRAS_DBG_ECO_CNTL, 0x00000880], [A6XXRegs.REG_A6XX_SP_CHICKEN_BITS, 0x00000430], + [A6XXRegs.REG_A6XX_SP_DBG_ECO_CNTL, 0], [A6XXRegs.REG_A6XX_UCHE_CLIENT_PF, 0x00000004], ], )) @@ -537,7 +537,6 @@ add_gpus([ wave_granularity = 2, fibers_per_sp = 128 * 16, magic_regs = dict( - SP_DBG_ECO_CNTL = 0x01000000, RB_DBG_ECO_CNTL = 0x04100000, RB_DBG_ECO_CNTL_blit = 0x04100000, HLSQ_DBG_ECO_CNTL = 0x0, @@ -552,6 +551,7 @@ add_gpus([ [A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL, 0x01008000], [A6XXRegs.REG_A6XX_GRAS_DBG_ECO_CNTL, 0], [A6XXRegs.REG_A6XX_SP_CHICKEN_BITS, 0x00000400], + [A6XXRegs.REG_A6XX_SP_DBG_ECO_CNTL, 0x01000000], [A6XXRegs.REG_A6XX_UCHE_CLIENT_PF, 0x00000004], ], )) @@ -570,7 +570,6 @@ add_gpus([ wave_granularity = 2, fibers_per_sp = 128 * 2 * 16, magic_regs = dict( - SP_DBG_ECO_CNTL = 0x03000000, RB_DBG_ECO_CNTL = 0x04100000, RB_DBG_ECO_CNTL_blit = 0x04100000, HLSQ_DBG_ECO_CNTL = 0x0, @@ -586,6 +585,7 @@ add_gpus([ [A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL, 0x01008000], [A6XXRegs.REG_A6XX_GRAS_DBG_ECO_CNTL, 0], [A6XXRegs.REG_A6XX_SP_CHICKEN_BITS, 0x00001400], + [A6XXRegs.REG_A6XX_SP_DBG_ECO_CNTL, 0x03000000], ], )) @@ -604,7 +604,6 @@ add_gpus([ highest_bank_bit = 15, macrotile_mode = 0, magic_regs = dict( - SP_DBG_ECO_CNTL = 0x0, RB_DBG_ECO_CNTL = 0x04100000, RB_DBG_ECO_CNTL_blit = 0x05100000, HLSQ_DBG_ECO_CNTL = 0x00080000, @@ -619,6 +618,7 @@ add_gpus([ [A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL, 0x00108000], [A6XXRegs.REG_A6XX_GRAS_DBG_ECO_CNTL, 0x00000880], [A6XXRegs.REG_A6XX_SP_CHICKEN_BITS, 0x00001430], + [A6XXRegs.REG_A6XX_SP_DBG_ECO_CNTL, 0], [A6XXRegs.REG_A6XX_UCHE_CLIENT_PF, 0x00000004], ], )) @@ -638,7 +638,6 @@ add_gpus([ highest_bank_bit = 15, macrotile_mode = 0, magic_regs = dict( - SP_DBG_ECO_CNTL = 0x0, RB_DBG_ECO_CNTL = 0x04100000, RB_DBG_ECO_CNTL_blit = 0x04100000, HLSQ_DBG_ECO_CNTL = 0x0, @@ -653,6 +652,7 @@ add_gpus([ [A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL, 0x00008000], [A6XXRegs.REG_A6XX_GRAS_DBG_ECO_CNTL, 0], [A6XXRegs.REG_A6XX_SP_CHICKEN_BITS, 0x00000420], + [A6XXRegs.REG_A6XX_SP_DBG_ECO_CNTL, 0], [A6XXRegs.REG_A6XX_UCHE_CLIENT_PF, 0x00000004], ], )) @@ -672,7 +672,6 @@ add_gpus([ highest_bank_bit = 15, macrotile_mode = 0, magic_regs = dict( - SP_DBG_ECO_CNTL = 0x0, RB_DBG_ECO_CNTL = 0x04100000, RB_DBG_ECO_CNTL_blit = 0x04100000, HLSQ_DBG_ECO_CNTL = 0x0, @@ -687,6 +686,7 @@ add_gpus([ [A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL, 0x00108000], [A6XXRegs.REG_A6XX_GRAS_DBG_ECO_CNTL, 0], [A6XXRegs.REG_A6XX_SP_CHICKEN_BITS, 0x00001430], + [A6XXRegs.REG_A6XX_SP_DBG_ECO_CNTL, 0], [A6XXRegs.REG_A6XX_UCHE_CLIENT_PF, 0x00000004], ], )) @@ -705,7 +705,6 @@ add_gpus([ fibers_per_sp = 128 * 2 * 16, highest_bank_bit = 16, magic_regs = dict( - SP_DBG_ECO_CNTL = 0x01000000, RB_DBG_ECO_CNTL = 0x04100000, RB_DBG_ECO_CNTL_blit = 0x04100000, HLSQ_DBG_ECO_CNTL = 0x0, @@ -721,6 +720,7 @@ add_gpus([ [A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL, 0x00108000], [A6XXRegs.REG_A6XX_GRAS_DBG_ECO_CNTL, 0], [A6XXRegs.REG_A6XX_SP_CHICKEN_BITS, 0x00001400], + [A6XXRegs.REG_A6XX_SP_DBG_ECO_CNTL, 0x01000000], [A6XXRegs.REG_A6XX_UCHE_CLIENT_PF, 0x00000004], ], )) @@ -745,7 +745,6 @@ add_gpus([ fibers_per_sp = 128 * 2 * 16, highest_bank_bit = 14, magic_regs = dict( - SP_DBG_ECO_CNTL = 0x00000006, RB_DBG_ECO_CNTL = 0x04100000, RB_DBG_ECO_CNTL_blit = 0x04100000, HLSQ_DBG_ECO_CNTL = 0x0, @@ -760,6 +759,7 @@ add_gpus([ [A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL, 0x05008000], [A6XXRegs.REG_A6XX_GRAS_DBG_ECO_CNTL, 0], [A6XXRegs.REG_A6XX_SP_CHICKEN_BITS, 0x00001400], + [A6XXRegs.REG_A6XX_SP_DBG_ECO_CNTL, 0x00000006], [A6XXRegs.REG_A6XX_UCHE_CLIENT_PF, 0x00000084], ], )) @@ -778,7 +778,6 @@ add_gpus([ fibers_per_sp = 128 * 2 * 16, highest_bank_bit = 16, magic_regs = dict( - SP_DBG_ECO_CNTL = 0x01000000, RB_DBG_ECO_CNTL = 0x04100000, RB_DBG_ECO_CNTL_blit = 0x04100000, HLSQ_DBG_ECO_CNTL = 0x0, @@ -793,6 +792,7 @@ add_gpus([ [A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL, 0x05008000], [A6XXRegs.REG_A6XX_GRAS_DBG_ECO_CNTL, 0], [A6XXRegs.REG_A6XX_SP_CHICKEN_BITS, 0x00001400], + [A6XXRegs.REG_A6XX_SP_DBG_ECO_CNTL, 0x01000000], [A6XXRegs.REG_A6XX_UCHE_CLIENT_PF, 0x00000084], ], )) @@ -811,7 +811,6 @@ add_gpus([ wave_granularity = 2, fibers_per_sp = 128 * 4 * 16, magic_regs = dict( - SP_DBG_ECO_CNTL = 0x6, RB_DBG_ECO_CNTL = 0x04100000, RB_DBG_ECO_CNTL_blit = 0x04100000, HLSQ_DBG_ECO_CNTL = 0x0, @@ -826,6 +825,7 @@ add_gpus([ [A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL, 0x05008000], [A6XXRegs.REG_A6XX_GRAS_DBG_ECO_CNTL, 0], [A6XXRegs.REG_A6XX_SP_CHICKEN_BITS, 0x00001400], + [A6XXRegs.REG_A6XX_SP_DBG_ECO_CNTL, 0x6], [A6XXRegs.REG_A6XX_UCHE_CLIENT_PF, 0x00000084], ], )) @@ -845,7 +845,6 @@ add_gpus([ fibers_per_sp = 128 * 2 * 16, highest_bank_bit = 16, magic_regs = dict( - SP_DBG_ECO_CNTL = 0x1200000, RB_DBG_ECO_CNTL = 0x100000, RB_DBG_ECO_CNTL_blit = 0x00100000, # ??? HLSQ_DBG_ECO_CNTL = 0x0, @@ -861,6 +860,7 @@ add_gpus([ [A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL, 0x04c00000], [A6XXRegs.REG_A6XX_GRAS_DBG_ECO_CNTL, 0], [A6XXRegs.REG_A6XX_SP_CHICKEN_BITS, 0x00001400], + [A6XXRegs.REG_A6XX_SP_DBG_ECO_CNTL, 0x1200000], [A6XXRegs.REG_A6XX_UCHE_CLIENT_PF, 0x00000084], ], )) @@ -894,7 +894,6 @@ add_gpus([ max_waves = 16, # has_early_preamble = True, # for VS/FS but not CS? magic_regs = dict( - SP_DBG_ECO_CNTL = 0x0, RB_DBG_ECO_CNTL = 0x100000, RB_DBG_ECO_CNTL_blit = 0x100000, HLSQ_DBG_ECO_CNTL = 0x02000000, @@ -909,6 +908,7 @@ add_gpus([ [A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL, 0x8000], [A6XXRegs.REG_A6XX_GRAS_DBG_ECO_CNTL, 0], [A6XXRegs.REG_A6XX_SP_CHICKEN_BITS, 0x00001400], + [A6XXRegs.REG_A6XX_SP_DBG_ECO_CNTL, 0], [A6XXRegs.REG_A6XX_UCHE_CLIENT_PF, 0x00000084], ], )) @@ -1020,7 +1020,6 @@ a7xx_gen3 = A7XXProps( ) a730_magic_regs = dict( - SP_DBG_ECO_CNTL = 0x10000000, RB_DBG_ECO_CNTL = 0x00000000, RB_DBG_ECO_CNTL_blit = 0x00000000, # is it even needed? RB_RBP_CNTL = 0x0, @@ -1043,6 +1042,7 @@ a730_raw_magic_regs = [ [A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E10, 0x00000000], [A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E11, 0x00000040], [A6XXRegs.REG_A7XX_SP_HLSQ_DBG_ECO_CNTL, 0x00008000], + [A6XXRegs.REG_A6XX_SP_DBG_ECO_CNTL, 0x10000000], [A6XXRegs.REG_A6XX_PC_MODE_CNTL, 0x0000003f], # 0x00001f1f in some tests [A6XXRegs.REG_A6XX_PC_DBG_ECO_CNTL, 0x20080000], [A6XXRegs.REG_A7XX_PC_UNKNOWN_9E24, 0x21fc7f00], @@ -1071,7 +1071,6 @@ a730_raw_magic_regs = [ ] a740_magic_regs = dict( - SP_DBG_ECO_CNTL = 0x10000000, RB_DBG_ECO_CNTL = 0x00000000, RB_DBG_ECO_CNTL_blit = 0x00000000, # is it even needed? # HLSQ_DBG_ECO_CNTL = 0x0, @@ -1095,6 +1094,7 @@ a740_raw_magic_regs = [ [A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E10, 0x00000000], [A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E11, 0x00000000], [A6XXRegs.REG_A7XX_SP_HLSQ_DBG_ECO_CNTL, 0x00000000], + [A6XXRegs.REG_A6XX_SP_DBG_ECO_CNTL, 0x10000000], # Blob uses 0x1f or 0x1f1f, however these values cause vertices # corruption in some tests. [A6XXRegs.REG_A6XX_PC_MODE_CNTL, 0x0000003f], @@ -1176,7 +1176,6 @@ add_gpus([ wave_granularity = 2, fibers_per_sp = 128 * 2 * 16, magic_regs = dict( - SP_DBG_ECO_CNTL = 0x10000000, RB_DBG_ECO_CNTL = 0x00000001, RB_DBG_ECO_CNTL_blit = 0x00000001, # is it even needed? RB_RBP_CNTL = 0x0, @@ -1198,6 +1197,7 @@ add_gpus([ [A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E10, 0x00000000], [A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E11, 0x00000000], [A6XXRegs.REG_A7XX_SP_HLSQ_DBG_ECO_CNTL, 0x00000000], + [A6XXRegs.REG_A6XX_SP_DBG_ECO_CNTL, 0x10000000], [A6XXRegs.REG_A6XX_PC_MODE_CNTL, 0x1f], [A6XXRegs.REG_A6XX_PC_DBG_ECO_CNTL, 0x00100000], [A6XXRegs.REG_A7XX_PC_UNKNOWN_9E24, 0x01585600], @@ -1275,6 +1275,7 @@ add_gpus([ [A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E10, 0x00000000], [A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E11, 0x00000080], [A6XXRegs.REG_A7XX_SP_HLSQ_DBG_ECO_CNTL, 0x00000000], + [A6XXRegs.REG_A6XX_SP_DBG_ECO_CNTL, 0x10000000], # Blob uses 0x1f or 0x1f1f, however these values cause vertices # corruption in some tests. [A6XXRegs.REG_A6XX_PC_MODE_CNTL, 0x0000003f], @@ -1319,7 +1320,6 @@ add_gpus([ wave_granularity = 2, fibers_per_sp = 128 * 2 * 16, magic_regs = dict( - SP_DBG_ECO_CNTL = 0x10000000, RB_DBG_ECO_CNTL = 0x00000001, RB_DBG_ECO_CNTL_blit = 0x00000000, # is it even needed? # HLSQ_DBG_ECO_CNTL = 0x0, @@ -1347,7 +1347,6 @@ add_gpus([ fibers_per_sp = 128 * 2 * 16, highest_bank_bit = 16, magic_regs = dict( - SP_DBG_ECO_CNTL = 0x10000000, RB_DBG_ECO_CNTL = 0x00000001, RB_DBG_ECO_CNTL_blit = 0x00000001, RB_RBP_CNTL = 0x0, @@ -1365,6 +1364,7 @@ add_gpus([ [A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_2, 0x00431800], [A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_3, 0x00800000], [A6XXRegs.REG_A7XX_SP_HLSQ_DBG_ECO_CNTL, 0x00000000], + [A6XXRegs.REG_A6XX_SP_DBG_ECO_CNTL, 0x10000000], [A6XXRegs.REG_A6XX_PC_MODE_CNTL, 0x3f1f], [A6XXRegs.REG_A6XX_PC_DBG_ECO_CNTL, 0x00100000], [A6XXRegs.REG_A7XX_PC_UNKNOWN_9E24, 0x01585600], diff --git a/src/freedreno/vulkan/tu_cmd_buffer.cc b/src/freedreno/vulkan/tu_cmd_buffer.cc index 4f498b3c460..85cfbaa814b 100644 --- a/src/freedreno/vulkan/tu_cmd_buffer.cc +++ b/src/freedreno/vulkan/tu_cmd_buffer.cc @@ -1962,8 +1962,6 @@ tu6_init_static_regs(struct tu_device *dev, struct tu_cs *cs) } tu_cs_emit_write_reg(cs, REG_A6XX_SP_NC_MODE_CNTL_2, 0); - tu_cs_emit_write_reg(cs, REG_A6XX_SP_DBG_ECO_CNTL, - phys_dev->info->a6xx.magic.SP_DBG_ECO_CNTL); tu_cs_emit_write_reg(cs, REG_A6XX_SP_PERFCTR_SHADER_MASK, 0x3f); if (CHIP == A6XX && !cs->device->physical_device->info->a6xx.is_a702) tu_cs_emit_write_reg(cs, REG_A6XX_TPL1_UNKNOWN_B605, 0x44); diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.cc b/src/gallium/drivers/freedreno/a6xx/fd6_emit.cc index 47900adfc96..ec15596b8c8 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.cc +++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.cc @@ -868,7 +868,6 @@ fd6_emit_static_non_context_regs(struct fd_context *ctx, fd_cs &cs) ncrb.add(A6XX_RB_DBG_ECO_CNTL(.dword = screen->info->a6xx.magic.RB_DBG_ECO_CNTL)); ncrb.add(A6XX_SP_NC_MODE_CNTL_2(.f16_no_inf = true)); - ncrb.add(A6XX_SP_DBG_ECO_CNTL(.dword = screen->info->a6xx.magic.SP_DBG_ECO_CNTL)); ncrb.add(A6XX_SP_PERFCTR_SHADER_MASK(.dword = 0x3f)); if (CHIP == A6XX && !screen->info->a6xx.is_a702) ncrb.add(TPL1_UNKNOWN_B605(CHIP, .dword = 0x44));