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freedreno/registers: pm4 updates for gen8

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Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
This commit is contained in:
Rob Clark 2025-10-27 11:11:51 -07:00 • committed by Marge Bot
parent fa45a48843
commit 39bf9c0222
2 changed files with 14 additions and 4 deletions
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12
src/freedreno/registers/adreno/adreno_pm4.xml
View file

@ -153,6 +153,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<value name="CACHE_FLUSH7" value="0x32" variants="A7XX-"/> <value name="CACHE_FLUSH7" value="0x32" variants="A7XX-"/>
<value name="CACHE_INVALIDATE7" value="0x33" variants="A7XX-"/> <value name="CACHE_INVALIDATE7" value="0x33" variants="A7XX-"/>
<value name="DEPTH_BUFFER_FLIP" value="0x3d" variants="A8XX-"/> <value name="DEPTH_BUFFER_FLIP" value="0x3d" variants="A8XX-"/>
<value name="CCH_FAST_CLEAR_CLEAN" value="0x1b" variants="A8XX-"/>
</enum> </enum>
<enum name="pc_di_primtype"> <enum name="pc_di_primtype">
@ -662,6 +663,12 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<value name="CP_CCHE_INVALIDATE" value="0x3a" variants="A7XX-"/> <value name="CP_CCHE_INVALIDATE" value="0x3a" variants="A7XX-"/>
<value name="CP_SCOPE_CNTL" value="0x6c" variants="A7XX-"/> <value name="CP_SCOPE_CNTL" value="0x6c" variants="A7XX-"/>
<value name="CP_SKIP_IB_MODE" value="0x27" variants="A7XX-"/>
<value name="CP_MEMORY_MAP_UPDATE" value="0x58" variants="A8XX-"/>
<value name="CP_BARRIER" value="0x59" variants="A8XX-"/>
</enum> </enum>
@ -1820,6 +1827,9 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
<!-- new in a8xx: --> <!-- new in a8xx: -->
<value value="32" name="RM8_DEPTH_PASS_START"/> <value value="32" name="RM8_DEPTH_PASS_START"/>
<value value="33" name="RM8_DEPTH_PASS_END"/> <value value="33" name="RM8_DEPTH_PASS_END"/>
<value value="34" name="RM8_SET_RENDER_TARGET"/>
<value value="35" name="RM8_PGMEM_ON"/>
<value value="36" name="RM8_PGMEM_OFF"/>
</enum> </enum>
<stripe varset="chip" variants="A6XX-A7XX"> <stripe varset="chip" variants="A6XX-A7XX">
<reg32 offset="0" name="0"> <reg32 offset="0" name="0">
@ -1865,8 +1875,8 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
<reg32 offset="0" name="0"> <reg32 offset="0" name="0">
<!-- if b8 is set, the low bits are interpreted differently (and b4 ignored) --> <!-- if b8 is set, the low bits are interpreted differently (and b4 ignored) -->
<bitfield name="MARKER_MODE" pos="8" type="set_marker_mode" addvariant="yes"/> <bitfield name="MARKER_MODE" pos="8" type="set_marker_mode" addvariant="yes"/>
<bitfield name="USES_GMEM" pos="7" type="boolean" varset="set_marker_mode" variants="SET_RENDER_MODE"/>
<bitfield name="MODE" low="0" high="6" type="a6xx_marker" varset="set_marker_mode" variants="SET_RENDER_MODE"/> <bitfield name="MODE" low="0" high="6" type="a6xx_marker" varset="set_marker_mode" variants="SET_RENDER_MODE"/>
<bitfield name="USES_GMEM" pos="7" type="boolean" varset="set_marker_mode" variants="SET_RENDER_MODE"/>
<bitfield name="IFPC_MODE" pos="0" type="a6xx_ifpc_mode" varset="set_marker_mode" variants="SET_IFPC_MODE"/> <bitfield name="IFPC_MODE" pos="0" type="a6xx_ifpc_mode" varset="set_marker_mode" variants="SET_IFPC_MODE"/>
<!-- idk if the RT w/a fields apply to a8xx as well --> <!-- idk if the RT w/a fields apply to a8xx as well -->
</reg32> </reg32>

6
src/freedreno/tests/reference/afuc_test_a7xx.asm
View file

@ -253,6 +253,7 @@ CP_SET_UNK_BIN_DATA:
CP_SET_VISIBILITY_OVERRIDE: CP_SET_VISIBILITY_OVERRIDE:
CP_SKIP_IB2_ENABLE_GLOBAL: CP_SKIP_IB2_ENABLE_GLOBAL:
CP_SKIP_IB2_ENABLE_LOCAL: CP_SKIP_IB2_ENABLE_LOCAL:
CP_SKIP_IB_MODE:
CP_SMMU_TABLE_UPDATE: CP_SMMU_TABLE_UPDATE:
CP_START_BIN: CP_START_BIN:
CP_TEST_TWO_MEMS: CP_TEST_TWO_MEMS:
@ -291,7 +292,6 @@ UNKN2:
UNKN3: UNKN3:
UNKN30: UNKN30:
UNKN32: UNKN32:
UNKN39:
UNKN43: UNKN43:
UNKN48: UNKN48:
UNKN5: UNKN5:
@ -423,6 +423,7 @@ CP_SET_UNK_BIN_DATA:
CP_SET_VISIBILITY_OVERRIDE: CP_SET_VISIBILITY_OVERRIDE:
CP_SKIP_IB2_ENABLE_GLOBAL: CP_SKIP_IB2_ENABLE_GLOBAL:
CP_SKIP_IB2_ENABLE_LOCAL: CP_SKIP_IB2_ENABLE_LOCAL:
CP_SKIP_IB_MODE:
CP_SMMU_TABLE_UPDATE: CP_SMMU_TABLE_UPDATE:
CP_START_BIN: CP_START_BIN:
CP_TEST_TWO_MEMS: CP_TEST_TWO_MEMS:
@ -462,7 +463,6 @@ UNKN2:
UNKN3: UNKN3:
UNKN30: UNKN30:
UNKN32: UNKN32:
UNKN39:
UNKN43: UNKN43:
UNKN48: UNKN48:
UNKN5: UNKN5:
@ -586,6 +586,7 @@ CP_SET_UNK_BIN_DATA:
CP_SET_VISIBILITY_OVERRIDE: CP_SET_VISIBILITY_OVERRIDE:
CP_SKIP_IB2_ENABLE_GLOBAL: CP_SKIP_IB2_ENABLE_GLOBAL:
CP_SKIP_IB2_ENABLE_LOCAL: CP_SKIP_IB2_ENABLE_LOCAL:
CP_SKIP_IB_MODE:
CP_SMMU_TABLE_UPDATE: CP_SMMU_TABLE_UPDATE:
CP_START_BIN: CP_START_BIN:
CP_TEST_TWO_MEMS: CP_TEST_TWO_MEMS:
@ -625,7 +626,6 @@ UNKN2:
UNKN3: UNKN3:
UNKN30: UNKN30:
UNKN32: UNKN32:
UNKN39:
UNKN43: UNKN43:
UNKN48: UNKN48:
UNKN5: UNKN5: