From 39bdf17d1932fcf4850c3535ab26fae64e09cd5d Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Mon, 17 Oct 2022 08:20:30 +0000 Subject: [PATCH] radv: use correct VGT_TESS_DISTRIBUTION settings on GFX11 Ported from RadeonSI. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Part-of: --- src/amd/vulkan/si_cmd_buffer.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index 565e22daa09..5c5140f7608 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -504,7 +504,13 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs) } } - if (physical_device->rad_info.gfx_level >= GFX9) { + if (physical_device->rad_info.gfx_level >= GFX11) { + /* ACCUM fields changed their meaning. */ + radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION, + S_028B50_ACCUM_ISOLINE(255) | S_028B50_ACCUM_TRI(255) | + S_028B50_ACCUM_QUAD(255) | S_028B50_DONUT_SPLIT_GFX9(24) | + S_028B50_TRAP_SPLIT(6)); + } else if (physical_device->rad_info.gfx_level >= GFX9) { radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION, S_028B50_ACCUM_ISOLINE(40) | S_028B50_ACCUM_TRI(30) | S_028B50_ACCUM_QUAD(24) | S_028B50_DONUT_SPLIT_GFX9(24) |