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intel/common: Prepare mi_builder tests to support Xe KMD

Browse source 
No functional change, just move i915 specific data to a struct
and check for kmd_type where appropriate.  This will make the
next patch (which adds Xe KMD support here) cleaner.

This patch had to make intel_kmd.h header C++ friendly so it
can use its symbols.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32194>
This commit is contained in:
Caio Oliveira 2024-11-18 20:55:35 -08:00 • committed by Marge Bot
parent 3735652be8
commit 3998602d0e
2 changed files with 160 additions and 134 deletions
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286
src/intel/common/tests/mi_builder_test.cpp
View file

@ -31,6 +31,7 @@
#include "c99_compat.h"
#include "common/intel_gem.h"
#include "dev/intel_device_info.h"
#include "dev/intel_kmd.h"
#include "intel_gem.h"
#include "isl/isl.h"
#include "drm-uapi/i915_drm.h"
@ -133,7 +134,6 @@ public:
}
int fd = -1;
uint32_t ctx_id = 0;
intel_device_info devinfo;
uint32_t batch_bo_handle = 0;
@ -143,9 +143,12 @@ public:
uint32_t batch_offset;
void *batch_map = NULL;
struct {
uint32_t ctx_id = 0;
#if GFX_VER < 8
std::vector<drm_i915_gem_relocation_entry> relocs;
std::vector<drm_i915_gem_relocation_entry> relocs;
#endif
} i915;
uint32_t data_bo_handle = 0;
#if GFX_VER >= 8
@ -181,14 +184,16 @@ mi_builder_test::SetUp()
if (fd < 0)
continue;
/* We don't really need to do this when running on hardware because
* we can just pull it from the drmDevice. However, without doing
* this, intel_dump_gpu gets a bit of heartburn and we can't use the
* --device option with it.
*/
int device_id;
ASSERT_TRUE(intel_gem_get_param(fd, I915_PARAM_CHIPSET_ID, &device_id))
<< strerror(errno);
if (intel_get_kmd_type(fd) == INTEL_KMD_TYPE_I915) {
/* We don't really need to do this when running on hardware because
* we can just pull it from the drmDevice. However, without doing
* this, intel_dump_gpu gets a bit of heartburn and we can't use the
* --device option with it.
*/
int device_id;
ASSERT_TRUE(intel_gem_get_param(fd, I915_PARAM_CHIPSET_ID, &device_id))
<< strerror(errno);
}
ASSERT_TRUE(intel_get_device_info_from_fd(fd, &devinfo, -1, -1));
if (devinfo.ver != GFX_VER ||
@ -205,101 +210,105 @@ mi_builder_test::SetUp()
ASSERT_TRUE(i < max_devices) << "Failed to find a DRM device";
drmFreeDevices(devices, max_devices);
ASSERT_TRUE(intel_gem_create_context(fd, &ctx_id)) << strerror(errno);
if (devinfo.kmd_type == INTEL_KMD_TYPE_I915) {
ASSERT_TRUE(intel_gem_create_context(fd, &i915.ctx_id)) << strerror(errno);
if (GFX_VER >= 8) {
/* On gfx8+, we require softpin */
int has_softpin;
ASSERT_TRUE(intel_gem_get_param(fd, I915_PARAM_HAS_EXEC_SOFTPIN, &has_softpin))
<< strerror(errno);
ASSERT_TRUE(has_softpin);
}
if (GFX_VER >= 8) {
/* On gfx8+, we require softpin */
int has_softpin;
ASSERT_TRUE(intel_gem_get_param(fd, I915_PARAM_HAS_EXEC_SOFTPIN, &has_softpin))
<< strerror(errno);
ASSERT_TRUE(has_softpin);
}
// Create the batch buffer
drm_i915_gem_create gem_create = drm_i915_gem_create();
gem_create.size = BATCH_BO_SIZE;
ASSERT_EQ(drmIoctl(fd, DRM_IOCTL_I915_GEM_CREATE,
(void *)&gem_create), 0) << strerror(errno);
batch_bo_handle = gem_create.handle;
// Create the batch buffer
drm_i915_gem_create gem_create = drm_i915_gem_create();
gem_create.size = BATCH_BO_SIZE;
ASSERT_EQ(drmIoctl(fd, DRM_IOCTL_I915_GEM_CREATE,
(void *)&gem_create), 0) << strerror(errno);
batch_bo_handle = gem_create.handle;
#if GFX_VER >= 8
batch_bo_addr = 0xffffffffdff70000ULL;
batch_bo_addr = 0xffffffffdff70000ULL;
#endif
if (devinfo.has_caching_uapi) {
drm_i915_gem_caching gem_caching = drm_i915_gem_caching();
gem_caching.handle = batch_bo_handle;
gem_caching.caching = I915_CACHING_CACHED;
ASSERT_EQ(drmIoctl(fd, DRM_IOCTL_I915_GEM_SET_CACHING,
(void *)&gem_caching), 0) << strerror(errno);
}
if (devinfo.has_caching_uapi) {
drm_i915_gem_caching gem_caching = drm_i915_gem_caching();
gem_caching.handle = batch_bo_handle;
gem_caching.caching = I915_CACHING_CACHED;
ASSERT_EQ(drmIoctl(fd, DRM_IOCTL_I915_GEM_SET_CACHING,
(void *)&gem_caching), 0) << strerror(errno);
}
if (devinfo.has_mmap_offset) {
drm_i915_gem_mmap_offset gem_mmap_offset = drm_i915_gem_mmap_offset();
gem_mmap_offset.handle = batch_bo_handle;
gem_mmap_offset.flags = devinfo.has_local_mem ?
I915_MMAP_OFFSET_FIXED :
I915_MMAP_OFFSET_WC;
ASSERT_EQ(drmIoctl(fd, DRM_IOCTL_I915_GEM_MMAP_OFFSET,
&gem_mmap_offset), 0) << strerror(errno);
if (devinfo.has_mmap_offset) {
drm_i915_gem_mmap_offset gem_mmap_offset = drm_i915_gem_mmap_offset();
gem_mmap_offset.handle = batch_bo_handle;
gem_mmap_offset.flags = devinfo.has_local_mem ?
I915_MMAP_OFFSET_FIXED :
I915_MMAP_OFFSET_WC;
ASSERT_EQ(drmIoctl(fd, DRM_IOCTL_I915_GEM_MMAP_OFFSET,
&gem_mmap_offset), 0) << strerror(errno);
batch_map = mmap(NULL, BATCH_BO_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED,
fd, gem_mmap_offset.offset);
ASSERT_NE(batch_map, MAP_FAILED) << strerror(errno);
batch_map = mmap(NULL, BATCH_BO_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED,
fd, gem_mmap_offset.offset);
ASSERT_NE(batch_map, MAP_FAILED) << strerror(errno);
} else {
drm_i915_gem_mmap gem_mmap = drm_i915_gem_mmap();
gem_mmap.handle = batch_bo_handle;
gem_mmap.offset = 0;
gem_mmap.size = BATCH_BO_SIZE;
gem_mmap.flags = 0;
ASSERT_EQ(drmIoctl(fd, DRM_IOCTL_I915_GEM_MMAP,
(void *)&gem_mmap), 0) << strerror(errno);
batch_map = (void *)(uintptr_t)gem_mmap.addr_ptr;
}
// Create the data buffer
gem_create = drm_i915_gem_create();
gem_create.size = DATA_BO_SIZE;
ASSERT_EQ(drmIoctl(fd, DRM_IOCTL_I915_GEM_CREATE,
(void *)&gem_create), 0) << strerror(errno);
data_bo_handle = gem_create.handle;
#if GFX_VER >= 8
data_bo_addr = 0xffffffffefff0000ULL;
#endif
if (devinfo.has_caching_uapi) {
drm_i915_gem_caching gem_caching = drm_i915_gem_caching();
gem_caching.handle = data_bo_handle;
gem_caching.caching = I915_CACHING_CACHED;
ASSERT_EQ(drmIoctl(fd, DRM_IOCTL_I915_GEM_SET_CACHING,
(void *)&gem_caching), 0) << strerror(errno);
}
if (devinfo.has_mmap_offset) {
drm_i915_gem_mmap_offset gem_mmap_offset = drm_i915_gem_mmap_offset();
gem_mmap_offset.handle = data_bo_handle;
gem_mmap_offset.flags = devinfo.has_local_mem ?
I915_MMAP_OFFSET_FIXED :
I915_MMAP_OFFSET_WC;
ASSERT_EQ(drmIoctl(fd, DRM_IOCTL_I915_GEM_MMAP_OFFSET,
&gem_mmap_offset), 0) << strerror(errno);
data_map = mmap(NULL, DATA_BO_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED,
fd, gem_mmap_offset.offset);
ASSERT_NE(data_map, MAP_FAILED) << strerror(errno);
} else {
drm_i915_gem_mmap gem_mmap = drm_i915_gem_mmap();
gem_mmap.handle = data_bo_handle;
gem_mmap.offset = 0;
gem_mmap.size = DATA_BO_SIZE;
gem_mmap.flags = 0;
ASSERT_EQ(drmIoctl(fd, DRM_IOCTL_I915_GEM_MMAP,
(void *)&gem_mmap), 0) << strerror(errno);
data_map = (void *)(uintptr_t)gem_mmap.addr_ptr;
}
} else {
drm_i915_gem_mmap gem_mmap = drm_i915_gem_mmap();
gem_mmap.handle = batch_bo_handle;
gem_mmap.offset = 0;
gem_mmap.size = BATCH_BO_SIZE;
gem_mmap.flags = 0;
ASSERT_EQ(drmIoctl(fd, DRM_IOCTL_I915_GEM_MMAP,
(void *)&gem_mmap), 0) << strerror(errno);
batch_map = (void *)(uintptr_t)gem_mmap.addr_ptr;
assert(!"TODO: Add Xe KMD support.");
}
// Start the batch at zero
batch_offset = 0;
// Create the data buffer
gem_create = drm_i915_gem_create();
gem_create.size = DATA_BO_SIZE;
ASSERT_EQ(drmIoctl(fd, DRM_IOCTL_I915_GEM_CREATE,
(void *)&gem_create), 0) << strerror(errno);
data_bo_handle = gem_create.handle;
#if GFX_VER >= 8
data_bo_addr = 0xffffffffefff0000ULL;
#endif
if (devinfo.has_caching_uapi) {
drm_i915_gem_caching gem_caching = drm_i915_gem_caching();
gem_caching.handle = data_bo_handle;
gem_caching.caching = I915_CACHING_CACHED;
ASSERT_EQ(drmIoctl(fd, DRM_IOCTL_I915_GEM_SET_CACHING,
(void *)&gem_caching), 0) << strerror(errno);
}
if (devinfo.has_mmap_offset) {
drm_i915_gem_mmap_offset gem_mmap_offset = drm_i915_gem_mmap_offset();
gem_mmap_offset.handle = data_bo_handle;
gem_mmap_offset.flags = devinfo.has_local_mem ?
I915_MMAP_OFFSET_FIXED :
I915_MMAP_OFFSET_WC;
ASSERT_EQ(drmIoctl(fd, DRM_IOCTL_I915_GEM_MMAP_OFFSET,
&gem_mmap_offset), 0) << strerror(errno);
data_map = mmap(NULL, DATA_BO_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED,
fd, gem_mmap_offset.offset);
ASSERT_NE(data_map, MAP_FAILED) << strerror(errno);
} else {
drm_i915_gem_mmap gem_mmap = drm_i915_gem_mmap();
gem_mmap.handle = data_bo_handle;
gem_mmap.offset = 0;
gem_mmap.size = DATA_BO_SIZE;
gem_mmap.flags = 0;
ASSERT_EQ(drmIoctl(fd, DRM_IOCTL_I915_GEM_MMAP,
(void *)&gem_mmap), 0) << strerror(errno);
data_map = (void *)(uintptr_t)gem_mmap.addr_ptr;
}
input = (char *)data_map + INPUT_DATA_OFFSET;
output = (char *)data_map + OUTPUT_DATA_OFFSET;
@ -343,12 +352,16 @@ mi_builder_test::TearDown()
EXPECT_EQ(err, 0) << "close batch bo failed";
}
if (ctx_id) {
struct drm_i915_gem_context_destroy destroy = {
.ctx_id = ctx_id,
};
err = intel_ioctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_DESTROY, &destroy);
EXPECT_EQ(err, 0) << "context destroy failed";
if (devinfo.kmd_type == INTEL_KMD_TYPE_I915) {
if (i915.ctx_id) {
struct drm_i915_gem_context_destroy destroy = {
.ctx_id = i915.ctx_id,
};
err = intel_ioctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_DESTROY, &destroy);
EXPECT_EQ(err, 0) << "context destroy failed";
}
} else {
assert(!"TODO: Add Xe KMD support.");
}
if (fd != -1)
@ -373,52 +386,56 @@ mi_builder_test::submit_batch()
if (batch_offset & 4)
mi_builder_emit(&b, GENX(MI_NOOP), noop);
drm_i915_gem_exec_object2 objects[2];
memset(objects, 0, sizeof(objects));
if (devinfo.kmd_type == INTEL_KMD_TYPE_I915) {
drm_i915_gem_exec_object2 objects[2];
memset(objects, 0, sizeof(objects));
objects[0].handle = data_bo_handle;
objects[0].relocation_count = 0;
objects[0].relocs_ptr = 0;
objects[0].handle = data_bo_handle;
objects[0].relocation_count = 0;
objects[0].relocs_ptr = 0;
#if GFX_VER >= 8 /* On gfx8+, we pin everything */
objects[0].flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS |
EXEC_OBJECT_PINNED |
EXEC_OBJECT_WRITE;
objects[0].offset = data_bo_addr;
objects[0].flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS |
EXEC_OBJECT_PINNED |
EXEC_OBJECT_WRITE;
objects[0].offset = data_bo_addr;
#else
objects[0].flags = EXEC_OBJECT_WRITE;
objects[0].offset = -1;
objects[0].flags = EXEC_OBJECT_WRITE;
objects[0].offset = -1;
#endif
objects[1].handle = batch_bo_handle;
objects[1].handle = batch_bo_handle;
#if GFX_VER >= 8 /* On gfx8+, we don't use relocations */
objects[1].relocation_count = 0;
objects[1].relocs_ptr = 0;
objects[1].flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS |
EXEC_OBJECT_PINNED;
objects[1].offset = batch_bo_addr;
objects[1].relocation_count = 0;
objects[1].relocs_ptr = 0;
objects[1].flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS |
EXEC_OBJECT_PINNED;
objects[1].offset = batch_bo_addr;
#else
objects[1].relocation_count = relocs.size();
objects[1].relocs_ptr = (uintptr_t)(void *)&relocs[0];
objects[1].flags = 0;
objects[1].offset = -1;
objects[1].relocation_count = i915.relocs.size();
objects[1].relocs_ptr = (uintptr_t)(void *)&i915.relocs[0];
objects[1].flags = 0;
objects[1].offset = -1;
#endif
drm_i915_gem_execbuffer2 execbuf = drm_i915_gem_execbuffer2();
execbuf.buffers_ptr = (uintptr_t)(void *)objects;
execbuf.buffer_count = 2;
execbuf.batch_start_offset = 0;
execbuf.batch_len = batch_offset;
execbuf.flags = I915_EXEC_HANDLE_LUT | I915_EXEC_RENDER;
execbuf.rsvd1 = ctx_id;
drm_i915_gem_execbuffer2 execbuf = drm_i915_gem_execbuffer2();
execbuf.buffers_ptr = (uintptr_t)(void *)objects;
execbuf.buffer_count = 2;
execbuf.batch_start_offset = 0;
execbuf.batch_len = batch_offset;
execbuf.flags = I915_EXEC_HANDLE_LUT | I915_EXEC_RENDER;
execbuf.rsvd1 = i915.ctx_id;
ASSERT_EQ(drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2,
(void *)&execbuf), 0) << strerror(errno);
ASSERT_EQ(drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2,
(void *)&execbuf), 0) << strerror(errno);
drm_i915_gem_wait gem_wait = drm_i915_gem_wait();
gem_wait.bo_handle = batch_bo_handle;
gem_wait.timeout_ns = INT64_MAX;
ASSERT_EQ(drmIoctl(fd, DRM_IOCTL_I915_GEM_WAIT,
(void *)&gem_wait), 0) << strerror(errno);
drm_i915_gem_wait gem_wait = drm_i915_gem_wait();
gem_wait.bo_handle = batch_bo_handle;
gem_wait.timeout_ns = INT64_MAX;
ASSERT_EQ(drmIoctl(fd, DRM_IOCTL_I915_GEM_WAIT,
(void *)&gem_wait), 0) << strerror(errno);
} else {
assert(!"TODO: Add Xe KMD support.");
}
}
uint64_t
@ -430,12 +447,13 @@ __gen_combine_address(mi_builder_test *test, void *location,
test->data_bo_addr : test->batch_bo_addr;
return addr_u64 + addr.offset + delta;
#else
assert(test->devinfo.kmd_type == INTEL_KMD_TYPE_I915);
drm_i915_gem_relocation_entry reloc = drm_i915_gem_relocation_entry();
reloc.target_handle = addr.gem_handle == test->data_bo_handle ? 0 : 1;
reloc.delta = addr.offset + delta;
reloc.offset = (char *)location - (char *)test->batch_map;
reloc.presumed_offset = -1;
test->relocs.push_back(reloc);
test->i915.relocs.push_back(reloc);
return reloc.delta;
#endif

8
src/intel/dev/intel_kmd.h
View file

@ -23,6 +23,10 @@
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
enum intel_kmd_type {
INTEL_KMD_TYPE_INVALID = 0,
INTEL_KMD_TYPE_I915,
@ -32,3 +36,7 @@ enum intel_kmd_type {
};
enum intel_kmd_type intel_get_kmd_type(int fd);
#ifdef __cplusplus
}
#endif