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radeonsi: set more state bits for disabled binning

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based on PAL

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15965>
This commit is contained in:
Marek Olšák 2022-03-22 09:03:37 -04:00 • committed by Marge Bot
parent 1999e927b0
commit 3985a1ac0f
1 changed files with 2 additions and 0 deletions
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2
src/gallium/drivers/radeonsi/si_state_binning.c
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@ -424,6 +424,8 @@ static void si_emit_dpbb_disable(struct si_context *sctx)
S_028C44_BIN_SIZE_X(bin_size.x == 16) | S_028C44_BIN_SIZE_Y(bin_size.y == 16) |
S_028C44_BIN_SIZE_X_EXTEND(bin_size_extend.x) |
S_028C44_BIN_SIZE_Y_EXTEND(bin_size_extend.y) | S_028C44_DISABLE_START_OF_PRIM(1) |
S_028C44_FPOVS_PER_BATCH(63) |
S_028C44_OPTIMAL_BIN_SELECTION(1) |
S_028C44_FLUSH_ON_BINNING_TRANSITION(1));
} else {
radeon_opt_set_context_reg(