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asahi: Implement indirect draws

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Passes dEQP-GLES31.functional.draw_indirect.*

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21273>
This commit is contained in:
Alyssa Rosenzweig 2023-02-12 12:19:58 -05:00
parent ad3375478c
commit 39774503b3
3 changed files with 29 additions and 11 deletions
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4
docs/features.txt
View file

@ -114,7 +114,7 @@ GL 3.3, GLSL 3.30 --- all DONE: freedreno, i965, nv50, nvc0, r600, radeonsi, llv
GL 4.0, GLSL 4.00 --- all DONE: freedreno/a6xx, i965/gen7+, nvc0, r600, radeonsi, llvmpipe, virgl, zink, d3d12
GL_ARB_draw_buffers_blend DONE (freedreno, i965/gen6+, nv50, softpipe, panfrost, v3d, asahi)
GL_ARB_draw_indirect DONE (freedreno, i965/gen7+, softpipe, v3d)
GL_ARB_draw_indirect DONE (freedreno, i965/gen7+, softpipe, v3d, asahi)
GL_ARB_gpu_shader5 DONE (freedreno/a6xx, i965/gen7+)
- 'precise' qualifier DONE (softpipe)
- Dynamically uniform sampler array indices DONE (softpipe)
@ -244,7 +244,7 @@ GLES3.1, GLSL ES 3.1 -- all DONE: freedreno/a5xx+, i965/hsw+, nvc0, r600, radeon
GL_ARB_arrays_of_arrays DONE (all drivers that support GLSL 1.30)
GL_ARB_compute_shader DONE (freedreno/a5xx+, i965/gen7+)
GL_ARB_draw_indirect DONE (freedreno, i965/gen7+)
GL_ARB_draw_indirect DONE (freedreno, i965/gen7+, asahi)
GL_ARB_explicit_uniform_location DONE (all drivers that support GLSL)
GL_ARB_framebuffer_no_attachments DONE (freedreno, i965/gen7+, softpipe)
GL_ARB_program_interface_query DONE (all drivers)

2
src/gallium/drivers/asahi/agx_pipe.c
View file

@ -1366,7 +1366,7 @@ agx_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
return is_deqp ? 7 : 0;
case PIPE_CAP_DRAW_INDIRECT:
return is_deqp;
return true;
case PIPE_CAP_VIDEO_MEMORY: {
uint64_t system_memory;

34
src/gallium/drivers/asahi/agx_state.c
View file

@ -2505,9 +2505,14 @@ agx_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info,
agx_pack(out, INDEX_LIST, cfg) {
cfg.primitive = prim;
cfg.index_count_present = true;
cfg.instance_count_present = true;
cfg.start_present = true;
if (indirect != NULL) {
cfg.indirect_buffer_present = true;
} else {
cfg.index_count_present = true;
cfg.start_present = true;
}
if (idx_size) {
cfg.restart_enable = info->primitive_restart;
@ -2526,18 +2531,31 @@ agx_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info,
out += AGX_INDEX_LIST_BUFFER_LO_LENGTH;
}
agx_pack(out, INDEX_LIST_COUNT, cfg)
cfg.count = draws->count;
out += AGX_INDEX_LIST_COUNT_LENGTH;
if (!indirect) {
agx_pack(out, INDEX_LIST_COUNT, cfg)
cfg.count = draws->count;
out += AGX_INDEX_LIST_COUNT_LENGTH;
}
agx_pack(out, INDEX_LIST_INSTANCES, cfg)
cfg.count = info->instance_count;
out += AGX_INDEX_LIST_INSTANCES_LENGTH;
agx_pack(out, INDEX_LIST_START, cfg) {
cfg.start = idx_size ? draws->index_bias : draws->start;
if (indirect) {
struct agx_resource *indirect_rsrc = agx_resource(indirect->buffer);
uint64_t address = indirect_rsrc->bo->ptr.gpu + indirect->offset;
agx_pack(out, INDEX_LIST_INDIRECT_BUFFER, cfg) {
cfg.address_hi = address >> 32;
cfg.address_lo = address & BITFIELD_MASK(32);
}
out += AGX_INDEX_LIST_INDIRECT_BUFFER_LENGTH;
} else {
agx_pack(out, INDEX_LIST_START, cfg) {
cfg.start = idx_size ? draws->index_bias : draws->start;
}
out += AGX_INDEX_LIST_START_LENGTH;
}
out += AGX_INDEX_LIST_START_LENGTH;
if (idx_size) {
agx_pack(out, INDEX_LIST_BUFFER_SIZE, cfg) {